UNISONIC TECHNOLOGIES CO., LTD
4051
8-CHANNEL ANALOG
MULTIPLEXERS/DEMULTIPLEXERS
SOP-16
CMOS IC
DESCRIPTION
UTC
4051
is single 8-channel analog multiplexers/demultiplexers
for application as digitally–controlled analog switches.
The device has three binary control inputs and an inhibit input. It
feature low ON impedance and very low OFF leakage current.
Control of analog signals up to the complete supply voltage range
can be achieved.
DIP-16
FEATURES
* Wide Analog Voltage Range: V
DD
–V
EE
= 3V~18V.
(Note: V
EE
must be≦V
SS
)
* Break-Before-Make Switching Eliminates Channel Overlap.
* Linearized Transfer Characteristics
* Implement an SP8T solid state switch effectively.
* Pin–to–Pin Replacement for CD4051
TSSOP-16
ORDERING INFORMATION
Ordering Number
Lead Free
4051L-S16-R
4051L-S16-T
4051L-P16-R
4051L-P16-T
4051L-D16-T
Halogen Free
4051G-S16-R
4051G-S16-T
4051G-P16-R
4051G-P16-T
4051G-D16-T
Package
SOP-16
SOP-16
TSSOP-16
TSSOP-16
DIP-16
Packing
Tape Reel
Tube
Tape Reel
Tube
Tube
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Copyright © 2012 Unisonic Technologies Co., LTD
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QW-R502-054.C
4051
PIN CONFIGURATION
CMOS IC
PIN DESCRIPTION
PIN No.
3
6
7
8
11,10,9
13,14,15,12,1,5,2,4
16
SYMBAL
X
INH
V
EE
V
SS
A,B,C
X0~X7
V
DD
I/O
I/O
I
NAME AND FUNCTION
Common Input/Output
Inhibit Inputs
Supply Voltage
Ground
Binary Control Inputs
Independent Inputs/Outputs
Positive Supply Voltage
I
I/O
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QW-R502-054.C
4051
ABSOLUTE MAXIMUM RATING
CMOS IC
PARAMETER
SYMBOL
RATINGS
UNIT
DC Supply Voltage (Referenced to V
EE
, V
SS
≧V
EE
)
V
DD
-0.5 ~ +18
V
Input or Output Voltage (DC or Transient)
V
IN
, V
OUT
-0.5 ~ V
DD
+0.5
V
(Referenced to V
SS
for Control Inputs and V
EE
for Switch I/O)
Input Current (DC or Transient), per Control Pin
I
IN
±10
mA
Switch Through Current
I
SW
±25
mA
Power Dissipation
500
mW
P
D
Derating above 65℃
7
mW/℃
Junction Temperature
T
J
125
℃
Operating Temperature
T
OPR
-40 ~ +125
℃
Storage Temperature
T
STG
-40 ~ +150
℃
Note: 1.Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.
ELECTRICAL CHARACTERISTICS
(T
A
=25℃, unless otherwise specified.)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
SUPPLY REQUIREMENTS (Voltages Referenced to V
EE
)
Power Supply Voltage Range
V
DD
V
DD
– 3.0≧V
SS
≧V
EE
3
18
V
DD
=5V
0.005
5
Control Inputs: V
IN
= V
SS
or V
DD
Quiescent Current per
I
Q
V
DD
=10V
Switch I/O: V
EE
≦V
I/O
≦V
DD
,
0.010
10
Package
ΔV
SW
≦500mV(Note
2)
V
DD
=15V
0.015
20
V
DD
=5V
(0.07 µA/kHz) f + I
Q
Total Supply Current
T
A
=25℃ only (The channel
I
D(AV)
component, (V
IN
-V
OUT
)/Ron, is
(Dynamic Plus Quiescent, V
DD
=10V
(0.20 µA/kHz) f + I
Q
Per Package)
not included.)
V
DD
=15V
(0.36 µA/kHz) f + I
Q
SWITCHES IN/OUT AND COMMONS OUT/IN -- X, Y, Z (Voltages Referenced to V
EE
)
Recommended Peak–to–Peak
V
I/O
Channel On or Off
0
V
DD
Voltage Into or Out of the Switch
Recommended Static or Dynamic
ΔV
SW
Channel On
0
600
Voltage Across the Switch
Output Offset Voltage
V
O(OFF)
V
IN
= 0V, No Load
10
V
DD
=5V
250
1050
ΔV
SW
≦500mV
V
IN
= V
IL
or V
IH
(Control),
ON Resistance
V
DD
=10V
120
500
R
ON
V
IN
= 0 to V
DD
(Switch)
V
DD
=15V
80
280
25
70
ΔON
Resistance Between V
DD
=5V
Any Two Channels in the
V
DD
=10V
10
50
ΔR
ON
Same Package
V
DD
=15V
10
45
V
IN
= V
IL
or V
IH
(Control)
Channel to Channel or Any
Off–Channel Leakage Current
I
OFF
±0.05
±100
One Channel, V
DD
=15V
Capacitance, Switch I/O
C
I/O
Inhibit = V
DD
10
Capacitance, Common O/I
C
O/I
Inhibit = V
DD
17
Pins Not Adjacent
0.15
Capacitance, Feedthrough
C
I/O
(Channel Off)
Pins Adjacent
0.47
UNIT
V
µA
µA
V
PP
mV
µV
Ω
Ω
nA
pF
pF
pF
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QW-R502-054.C
4051
ELECTRICAL CHARACTERISTICS(Cont.)
PARAMETER
SYMBOL
TEST CONDITIONS
CONTROL INPUTS – INHIBIT A, B, C (Voltages Referenced to V
SS
)
V
DD
=5V
R
ON
= per spec,
Low Level Input Voltage
V
DD
=10V
V
IL
I
OFF
= per spec
V
DD
=15V
V
DD
=5V
R
ON
= per spec,
High Level Input Voltage
V
DD
=10V
V
IH
I
OFF
= per spec
V
DD
=15V
Input Leakage Current
I
LEAK
V
IN
= 0 or V
DD
, V
DD
=15V
Input Capacitance
C
IN
MIN
TYP
2.25
4.50
4.0
2.75
5.5
8.25
±0.00001
5.0
CMOS IC
MAX
1.5
3.0
UNIT
V
6.75
3.5
7
11
V
±0.1
7.5
µA
pF
DYNAMIC ELECTRICAL CHARACTERISTICS
(C
L
= 50pF, T
A
=25℃, V
EE
≦V
SS
, unless otherwise specified)
PARAMETER
Propagation Delay Times
Switch Input to Switch
Output (R
L
= 10kΩ)
Inhibit to Output
SYMBOL
t
PLH,
t
PHL
t
PHZ,
t
PLZ
t
PZH,
t
PZL
t
PLH,
t
PHL
THD
V
DD
-V
EE
V
DC
5
10
15
5
10
15
5
10
15
10
TEST CONDITIONS
t
PLH
, t
PHL
=(0.17 ns/pF)C
L
+ 26.5ns
t
PLH
, t
PHL
=(0.08 ns/pF)C
L
+ 11ns
t
PLH
, t
PHL
=(0.06 ns/pF)C
L
+ 9ns
(R
L
=10kΩ, V
EE
=V
SS
)
Output “1” or “0” to High Impedance,
or High Impedance to “1” or “0” Level
R
L
= 10kΩ, V
EE
= V
SS
MIN
TYP
35
15
12
350
170
140
360
160
120
0.07
MAX
90
40
30
700
340
280
720
320
240
UNIT
ns
ns
Control Input to Output
Total Harmonic Distortion
ns
R
L
= 10KΩ, f = 1 kHz, Vin = 5 V
PP
%
R
L
= 1kΩ, V
IN
= 1/2 (V
DD
–V
EE
) p–p,
17
MHz
Bandwidth
BW
10
C
L
= 50pF, 20 Log (V
OUT
/V
IN
) = -3dB)
R
L
=1KΩ, V
IN
= 1/2 (V
DD
–V
EE
) p–p
Off Channel Feedthrough
10
-50
dB
Attenuation
f
IN
= 4.5 MHz
R
L
= 1kΩ, V
IN
= 1/2 (V
DD
–V
EE
) p–p
-50
dB
Channel Separation
10
f
IN
= 3MHz
R
1
= 1kΩ, R
L
= 10kΩ Control
Crosstalk, Control Input to
10
75
mV
Common O/I
t
TLH
= t
THL
= 20ns, Inhibit = V
SS
Note: 1. Data of “TYP” is intended as an indication of the IC’s potential performance.
2. For voltage drops across the switch(ΔV
SW
)>600mV (>300mV at high temperature), excessive V
DD
current
may be drawn, i.e. the current out of the switch may contain both V
DD
and switch input components. The
reliability of the device will be unaffected unless the Maximum Ratings are exceeded.
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QW-R502-054.C
4051
TEST CIRCUIT
CMOS IC
V
DD
IN/OUT
V
DD
V
DD
OUT/IN
V
EE
V
DD
LEVEL
CONVERTED
CONTROL
IN/OUT
OUT/IN
V
EE
CONTROL
Switch Circuit Schematic
TRUTH TABLE
Control Inputs
INHIBIT C
B
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
x
A
0
1
0
1
0
1
0
1
x
ON Switches
X0
X1
X2
X3
X4
X5
X6
X7
None
1
x
x = Don’t Care
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QW-R502-054.C
FPGA/CPLD
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