Philips Semiconductors
Product specification
1.4 GHz I
2
C-bus controlled synthesizer
FEATURES
•
Complete 1.4 GHz single chip system
•
Three PNP band switch buffers (20 mA)
•
Four bus-controlled bidirectional ports (NPN
open-collector outputs); only one port in 16-pin version
•
33 V tuning voltage output
•
In-lock detector
•
5-step ADC
•
Mixer-Oscillator (M/O) band switch output
•
15-bit programmable divider
•
Programmable reference divider ratio (512, 640
or 1024)
•
Programmable charge-pump current (50 or 250
µA)
•
Varicap drive disable
•
I
2
C-bus format
– address plus 4 data bytes transmission (write mode)
– address plus 1 status byte transmission (read mode)
– three independent addresses
•
Low power and low radiation.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
TSA5522M
TSA5522T
SSOP20
SO16
DESCRIPTION
plastic shrink small outline package; 20 leads; body width 4.4 mm
plastic small outline package; 16 leads; body width 3.9 mm
APPLICATIONS
•
TV tuners and front-ends
•
VCR tuners.
TSA5522
VERSION
SOT266-1
SOT109-1
1996 Jan 23
2
Philips Semiconductors
Product specification
1.4 GHz I
2
C-bus controlled synthesizer
QUICK REFERENCE DATA
SYMBOL
V
CC1
V
CC2
I
CC1
I
CC2
f
RF
V
i(RF)
PARAMETER
supply voltage (+5 V)
band switch supply voltage (+12 V)
supply current
band switch supply current
RF input frequency
RF input voltage
f
i
= 80 to 150 MHz
f
i
= 150 to 1000 MHz
f
i
= 1000 to 1400 MHz
f
xtal
I
o(PNP)
I
o(NPN)
T
amb
T
stg
Note
1. One band switch buffer ON; I
o
= 20 mA.
GENERAL DESCRIPTION
(see Fig.1)
The device is a single chip PLL frequency synthesizer
designed for TV and VCR tuning systems. The circuit
consists of a divide-by-eight prescaler with its own
preamplifier, a 15-bit programmable divider, a crystal
oscillator and its programmable reference divider and a
phase/frequency detector combined with a charge-pump
which drives the tuning amplifier, including 33 V output.
Three high-current PNP band switch buffers are provided
for band switching together with four open-collector NPN
outputs (only one open-collector output on 16-pin
devices). These ports can also be used as input ports [one
Analog-to Digital Converter (ADC) and three general
purpose I/O ports (not available on 16-pin devices)]. An
output is provided to control a Philips mixer/oscillator IC in
combination with the PNP buffers state.
Depending on the reference divider ratio (512, 640
or 1024), the phase comparator operates at 3.90625 kHz,
6.25 kHz or 7.8125 kHz with a 4 MHz crystal. The LOCK
detector bit FL is set to logic 1 when the loop is locked and
is read on the SDA line (status byte) during a read
operation.
crystal oscillator input frequency
PNP band switch buffers output current
NPN open-collector output current
operating ambient temperature
storage temperature (IC)
note 1
CONDITIONS
MIN.
4.5
V
CC1
−
−
64
−
25
−
28
−
26
−
−
−
−20
−40
−
12
22
27
−
−
−
−
4
20
20
−
−
TYP.
TSA5522
MAX.
5.5
13.5
30
32
1400
3
3
3
−
25
25
+85
+150
UNIT
V
V
mA
mA
MHz
dBm
dBm
dBm
MHz
mA
mA
°C
°C
The ADC is available for digital AFC control. The ADC
code is read during a read operation on the I
2
C-bus. The
ADC input is combined with the port P6. In the TEST
mode, this port is also used as a TEST output for f
ref
and
1
⁄
f
2 div
(see Table 4).
I
2
C-bus format
Five serial bytes (including address byte) are required to
address the device, select the VCO frequency, program
the ports, set the charge-pump current and the reference
divider ratio. The device has three independent I
2
C-bus
addresses selected by applying a specific voltage on AS
input (see Table 3). The general address C2 is always
valid.
1996 Jan 23
3
Philips Semiconductors
Product specification
1.4 GHz I
2
C-bus controlled synthesizer
PINNING
SYMBOL
V
CC1
RF1
RF2
BS
V
EE
V
CC2
n.c.
P2
P1
P0
CP
V
tune
P6
P7
P5
P4
SCL
SDA
AS
XTAL
SO16
1
2
3
4
5
6
−
7
8
9
10
11
12
−
−
−
13
14
15
16
SSOP20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
voltage supply (+5 V)
RF signal input 1
RF signal input 2
band switch output to mixer/oscillator drive
ground
voltage supply (+12 V)
not connected
PNP band switch buffer output 2
PNP band switch buffer output 1
PNP band switch buffer output 0
charge-pump output
tuning voltage output
NPN open-collector output/ADC input
NPN open-collector output/comparator input
NPN open-collector output/comparator input
NPN open-collector output/comparator input
serial clock input
serial data input/output
address selection input
crystal oscillator input
DESCRIPTION
TSA5522
handbook, halfpage
handbook, halfpage
V CC1
RF1
RF2
BS
V EE
V CC2
n.c.
P2
P1
1
2
3
4
5
20 XTAL
19 AS
18 SDA
17 SCL
16 P4
V CC1 1
RF1 2
RF2 3
BS 4
16 XTAL
15 AS
14 SDA
13 SCL
TSA5522T
V EE 5
V CC2 6
P2 7
P1 8
MLD225
TSA5522M
6
7
8
9
15 P5
14 P7
13 P6
12 V tune
11 CP
MLD230
12 P6
11 V tune
10 CP
9 PO
P0 10
Fig.2 Pin configuration (SO16).
Fig.3 Pin configuration (SSOP20).
1996 Jan 23
5
FPGA/CPLD
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