Laser Processed Logic Device Family
Key Features
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Laser Processed Logic Device (LPLD) technology offers
the ultimate combination of performance, flexibility, and
low cost
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Functionally, architecturally, and electrically compatible
with industry-standard Altera
®
MAX
®
7000
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High Density
-
-
-
3,700 Usable gates
192 Macrocells
152 Maximum user I/O pins
CL7192E
CL7192S
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Laser fuse technology provides very fast, dense
interconnect routing
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Low current consumption
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Supports 3.3 volt or 5.0 volt I/O operation
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Alpha particle immune
CL7000 Product Family Overview
Parameter
Useable Gates
Macrocells
Logic Blocks
Max user I/O pins
Speed Grades
CL7128E
CL7128S
2,500
128
8
100
-5, -6, -7, -10,
-12, -15, -20
84-pin PLCC
100-pin TQFP
100-pin PQFP
160-pin PQFP
CL7160E
CL7160S
3,200
160
10
104
-5, -6, -7, -10,
-12, -15, -20
84-pin PLCC
100-pin TQFP
100-pin PQFP
160-pin PQFP
CL7192E
CL7192S
3,750
192
12
124
-6, -7, -10,
-12, -15, -20
160-pin PQFP
CL7256E
CL7256S
5,000
256
16
164
-6, -7, -10,
-12, -15, -20
160-pin PQFP
208-pin PQFP
208-pin RQFP
7K tbl 01B
Packages
December 2000
Page 1
CL7192E and CL7192S Laser Processed Logic Devices
Description
The Clear Logic CL7000 Laser Processed Logic Device (LPLD
®
)
family offers the ultimate combination of performance,
flexibility, and cost. This family is a system level second source
to Altera MAX
®
7000, 7000E, and 7000S products. For designs
not requiring in-system reprogrammability, design verification
can be performed using the programmable Altera devices, and
Clear Logic LPLDs can be used for low cost, high volume
production.
Clear Logics innovative laser-based technology eliminates NRE
costs, test vector development, ordering minimums and long lead
times. No re-simulation or re-layout is required, as the device
uses a cell-based, PLD-like architecture. Clear Logics NoFault
®
technology ensures complete test coverage through the use of
specialized testing modes which are transparent to the user.
The Clear Logic CL7000 Laser Processed Logic Device family is
based upon a large array of macrocells. Each macrocell
contains a logic array with five product terms, a product-term
select matrix, and a configurable register. A group of sixteen
macrocells forms a block.
Laser-configured metal fuses
implement logical functions and control signal routing.
Laser configuration provides reduced cost and enhanced
performance. These inherent performance benefits include
extremely consistent propagation delays, reduced power
consumption, and improved immunity to noise and upset events.
Additional
Information
For further information on designing with the CL7000 LPLD
family, please consult the following documents:
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AN-01: Requesting a First Article. This document provides
instructions on how to submit a bitstream file for
generation of first articles.
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AN-02: Clear Logic Packaging Guide. This document provides
specifications and drawings for packages used by the CL7000
family.
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AN-09: CL7000 Technology White Paper. This document
outlines the technologies employed by the CL7000 LPLD
family.
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AN-10: Calculating CL7000 Power Consumption. This
document provides guidelines for calculating power
consumption based on design characteristics.
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AN-11: CL7000 Test Methodology. This document discribes
how Clear Logic provides 100% stuck-at fault coverage.
Page 2
CL7192E and CL7192S Laser Processed Logic Devices
Macrocell Diagram
Local Array
Global Global
Clear Clocks
Fast Input
Select
Configurable
Register
Register
Bypass
to I/O
Control
Block
from
I/O pin
2
Parallel Logic
Expanders
D
PRN
Q
Product
Term
Select
Matrix
Clear
Select
Clock/
Enable
Select
VCC
ENA
CLRN
Shared Logic
Expanders
36 Signals
from LIA
16 Expander
Product Terms
to LIA
7K drw 01
Pin Configuration
Pin Name
INPUT/GCLK1
INPUT/GCLRn
INPUT/OE1
INPUT/OE2/GCLK2
TDI
TMS
TCK
TDO
GND
VCCINT
VCCIO
NC (No Connect)
Total user I/O pins
160 pin PQFP
139
141
140
142
146
23
98
135
3, 18, 32, 47, 57, 64, 66, 81, 96, 111, 126, 138, 143, 148
56, 65, 137, 144
10, 25, 40, 55, 74, 89, 103, 118, 133, 155
1, 11, 39, 54, 67, 82, 110, 120
120
7192 tbl 01
Page 5
FPGA/CPLD
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