[AK4128A]
AK4128A
8ch 216kHz / 24-Bit Asynchronous SRC
GENERAL DESCRIPTION
The AK4128A is an 8ch digital sample rate converter (SRC). The input sample rate ranges from 8kHz to
216kHz. The output sample rate is from 8kHz to 216kHz. The AK4128A has an internal Oscillator and
does not need any external master clocks. It contributes simplifying a system configuration. The AK4128A
supports master mode and TDM data interface, enabling simultaneous input of asynchronous stereo
data. The AK4128A is suitable for the application interfacing to different sample rates such as
multi-channel high-end Car Audio Systems and DVD recorders.
FEATURES
•
8 channels input/output
•
Asynchronous Sample Rate Converter
•
Input Sample Rate Range (FSI): 8kHz
∼
216kHz
•
Output Sample Rate Range (FSO): 8kHz
∼
216kHz
•
Input to Output Sample Rate Ratio: 1/6 to 6
•
THD+N:
−130dB
•
Dynamic Range: 140dB (A-weighted)
•
I/F format: MSB justified, LSB justified and I
2
S compatible and TDM
•
Oscillator for Internal Operation Clock
•
Clock for Master mode: 128/256/384/512/768fso
•
On-chip X’tal oscillator
•
Digital De-emphasis Filter (32kHz, 44.1kHz and 48kHz)
•
Soft Mute Function
•
SRC Bypass mode (Master/Slave)
•
μP
Interface: I²C bus
•
Power Supply: AVDD, DVDD1-4: 3.0
∼
3.6V (typ. 3.3V)
•
Ta =
−20 ∼
85°C (AK4128AEQ),
−40 ∼
85°C (AK4128AVQ)
•
Package: 64LQFP
MS1242-E-01
-1-
2011/06
[AK4128A]
■
Compatibility with AK4126
(1) Specifications
Parameter
Stereo Inputs
Asynchronous Mode
Internal Clock
AK4126
Not Available
Synchronous Mode Only
AK4128A
Available
The INAS pin controls synchronous and
asynchronous modes.
Internal PLL
Internal Regulator + Internal Oscillator
The PLL2-0 pins must be set
PLL reference clock select is not needed since
according to the PLL reference clock.
internal oscillator generates the clock.
#61 pin: A pin for external devices of
#61 pin: A capacitor pin for the internal regulator.
PLL filter.
Not Available
Available
Controlled by CM2-0 pins or BYPS bit.
Not Available
Available
Controlled by CM2-0 pins
192kHz
216kHz
64fs
Not Available
Not Available
Not Available
All channels are controlled together.
256fs
Available
Available
Available
Controlled by IDIF2-0 pins or IDIF2-0 bits (Input)
Controlled by TDM pin (Output)
Individual Setting Available
Individual setting is available by setting SMUTE4-1
bits in serial control mode.
Individual Setting Available
Individual setting is available by DEM41-40,
31-30, 21-20, 11-10 bits in serial control mode.
Individual Setting Available
Individual setting is available by IDIF42-40, 32-30,
22-20, 12-10 bits in serial control mode.
Available
Parallel and Serial control modes are selected by the
SPB pin.
FSI:FSO Ratio Change Detect
Detects over-current/voltage of the 1.8V outputs.
Bypass Mode
Master Mode for
Output Ports
Maximum FSI and
FSO
Maximum IBICK and
OBICK Frequency
X’tal Oscillator
Master Clock Output
TDM Mode
Soft Mute
De-emphasis Filter
All channels are controlled together.
Audio Format for
Input port.
I2C
All channels are controlled together.
Not Available
UNLOCK pin
Detects PLL unlock.
MS1242-E-01
-3-
2011/06
Linux and Android
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