[AK4425A]
AK4425A
192kHz 24-Bit Stereo
ΔΣ
DAC with 2Vrms Output
GENERAL DESCRIPTION
The AK4425A is a 5V 24-bit stereo DAC with an integrated 2Vrms output buffer. A charge pump in the
buffer develops an internal negative power supply rail that enables a ground-referenced 2Vrms output.
Using AKM’s multi bit modulator architecture, the AK4425A delivers a wide dynamic range while
preserving linearity for improved THD+N performance. The AK4425A integrates a combination of
switched-capacitor and continuous-time filters, increasing performance for systems with excessive clock
jitter. The 24-bit word length and 192kHz sampling rate make this part ideal for a wide range of consumer
audio applications, such as DVD, AV receiver system and set-top boxes. The AK4425A is offered in a
space saving 16pin TSSOP package.
FEATURES
Sampling Rate Ranging from 8kHz to 192kHz
128 times Oversampling (Normal Speed Mode)
64 times Oversampling (Double Speed Mode)
32 times Oversampling (Quad Speed Mode)
24-Bit 8 times FIR Digital Filter
Switched-Capacitor Filter with High Tolerance to Clock Jitter
Single Ended 2Vrms Output Buffer
Digital De-emphasis Filter: 32kHz, 44.1kHz or 48kHz
Soft mute
Digital Attenuator (Linear 256 Step)
Control I/F: 3-wire
Audio I/F format: 24Bit MSB justified, 24/20/16 LSB justified or
I
2
S compatible
Master clock: 256fs, 384fs, 512fs, 768fs or 1152fs (Normal Speed Mode)
128fs, 192fs, 256fs or 384fs (Double Speed Mode)
128fs, 192fs (Quad Speed Mode)
THD+N: -91dB
Dynamic Range: 106dB
Automatic Power-on Reset Circuit
Power supply: +4.5
∼
+5.5V
Ta = -20 to 85°C
Small Package: 16pin TSSOP (6.4mm x 5.0mm)
MS1127-E-01
-1-
2011/03
[AK4425A]
MCLK
AVDD
CSN
CCLK
CDTI
Control
Interface
De-emphasis
Control
Clock
Divider
VSS2
LRCK
BICK
SDTI
Audio
Data
Interface
8X
Interpolator
8X
Interpolator
Charge
Pump
CP
CN
ΔΣ
Modulator
ΔΣ
Modulator
SCF
LPF
SCF
LPF
AOUTL
AOUTR
VEE
VSS1
VDD
1μ
1μ
Block Diagram
MS1127-E-01
-2-
2011/03
[AK4425A]
■
Ordering Guide
AK4425AET
AKD4425A
-20
∼
+85°C
16pin TSSOP (0.65mm pitch)
Evaluation Board for AK4425A
■
Pin Layout
VDD
MCLK
BICK
SDTI
LRCK
CSN
CCLK
CDTI
1
2
3
4
5
6
7
8
16
15
14
VSS1
CP
CN
VEE
AOUTL
VSS2
AVDD
AOUTR
AK4425A
Top
View
13
12
11
10
9
■
Compatibility with the AK4426
Functions
Power Supply
DC Offset
THD+N
DR
DEM
SMUTE
Digital ATT
I/F Format
Control I/F
Operating Temperature
AK4426
+4.5
∼
+5.5V
± 8mV
-91dB
106dB
X
X
X
24-bit MSB/ I²S/
24,20,16bitLSB
I²C
ET: -20
∼
+85°C
VT: -40
∼
+85°C
AK4425A
± 5mV
-: Not available
X: Available
MS1127-E-01
-3-
2011/03
[AK4425A]
PIN/FUNCTION
Function
Digital Circuit and Charge Pump Circuit Power Supply Pin: 4.5V∼5.5V
Master Clock Input Pin
2
MCLK
I
An external TTL clock must be input on this pin.
3
Audio Serial Data Clock Pin
BICK
I
4
Audio Serial Data Input Pin
SDTI
I
5
L/R Clock Pin
LRCK
I
6
Chip Select Pin
CSN
I
7
Control Clock input Pin
CCLK
I
8
Control Data Input Pin
CDTI
I
Rch Analog Output Pin
9
AOUTR
O
When power down, outputs VSS(0V, typ).
10
Analog Block Power Supply Pin: 4.5V∼5.5V
AVDD
-
11
Ground Pin2
VSS2
-
Lch Analog Output Pin
12
AOUTL
O
When power down, outputs VSS(0V, typ).
Negative Voltage Output Pin
Connect to VSS1 with a 1.0μF capacitor which is low ESR (Equivalent
13
Series Resistance) over all temperature range. When this capacitor has the
VEE
O
polarity, the positive polarity pin must be connected to the VSS1 pin. Non
polarity capacitors can also be used.
Negative Charge Pump Capacitor Terminal Pin
Connect to CP with a 1.0μF capacitor which is low ESR (Equivalent Series
14
Resistance) over all temperature range. When this capacitor has the polarity,
CN
I
the positive polarity pin must be connected to the CP pin. Non polarity
capacitors can also be used.
Positive Charge Pump Capacitor Terminal Pin
Connect to CN with a 1.0μF capacitor which is low ESR (Equivalent Series
15
Resistance) over all temperature range. When this capacitor has the polarity,
CP
I
the positive polarity pin must be connected to the CP pin. Non polarity
capacitors can also be used.
16
Ground Pin1
VSS1
-
Note: All input pins except for the CN pin should not be left floating.
No.
1
Pin Name
VDD
I/O
-
MS1127-E-01
-4-
2011/03
[AK4425A]
ABSOLUTE MAXIMUM RATINGS
(VSS1=VSS2=0V;
Note 1)
Parameter
Power Supply
Symbol
VDD
CVDD
IIN
VIND
Ta
Tstg
min
-0.3
-0.3
-
-0.3
-20
-65
max
+6.0
+6.0
±10
VDD+0.3
85
150
Units
V
V
mA
V
°C
°C
Input Current (any pins except for supplies)
Input Voltage
Ambient Operating Temperature
Storage Temperature
Note 1. All voltages with respect to ground.
Note 2. VSS1, VSS2 connect to the same analog ground.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS1=VSS2=0V;
Note 1)
Parameter
Power Supply
Note 3. AVDD should be equal to VDD
*AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
Symbol
VDD
AVDD
min
+4.5
typ
+5.0
VDD
max
+5.5
Units
V
MS1127-E-01
-5-
2011/03
京公网安备 11010802033920号
EEWORLD
