PI7C7100
3-Port
PCI Bridge
Pericom Semiconductor Corporation
The Complete Interface Solution
2380 Bering Drive, San Jose, California 95131
Telephone: 1-877-PERICOM, (1-877-737-4266)
Fax: (408) 435-1100, E-mail: nolimits@pericom.com
Internet: http://www.pericom.com
© 2000 Pericom Semiconductor Corporation
05/08/00
ADVANCE INFORMATION
65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI7C7100
3-Port PCI Bridge
LIFE SUPPORT POLICY
Pericom Semiconductor Corporations products are not authorized for use as critical components in life support devices or
systems unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an
officer of PSC.
1.Life support devices or systems are devices or systems which:
a) are intended for surgical implant into the body or
b) support or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided
in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.Pericom Semiconductor
Corporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve
design or performance and to supply the best possible product. Pericom Semiconductor does not assume any responsibility
for use of any circuitry described other than the circuitry embodied in a Pericom Semiconductor product. The Company makes
no representations that circuitry described herein is free from patent infringement or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under any patent, patent rights or other rights, of Pericom
Semiconductor Corporation.
All other trademarks are of their respective companies.
ii
05/08/00
ADVANCE INFORMATION
765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI7C7100
3-Port PCI Bridge
Table of Contents
1.
2.
3.
3.1
3.2
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.2.6
4.
4.1
4.2
4.3
4.4
4.5
4.5.1
4.5.2
4.5.3
4.5.4
4.5.5
4.5.6
4.6
4.6.1
4.6.2
4.6.3
4.6.4
4.6.5
4.6.6
4.7
4.7.1
4.7.2
4.7.3
4.7.4
4.8
4.8.1
4.8.2
4.8.3
4.8.4
Introduction/Product Features
............................................................................................................................... 1
PI7C7100 Block Diagram
...................................................................................................................................... 3
Signal Definitions
................................................................................................................................................... 4
Signal Types ............................................................................................................................................................ 4
Signals ...................................................................................................................................................................... 4
Primary Bus Interface Signals .................................................................................................................................. 4
Secondary Bus Interface Signals ............................................................................................................................. 6
Clock Signals ............................................................................................................................................................ 8
Miscellaneous Signals ............................................................................................................................................. 8
JTAG Boundary Scan Signals .................................................................................................................................. 9
Power and Ground .................................................................................................................................................... 9
PCI Bus Operation
................................................................................................................................................ 10
Types of Transactions ........................................................................................................................................... 10
Single Address Phase ............................................................................................................................................ 11
Device Select (DEVSEL#) Generation .................................................................................................................... 11
Data Phase ............................................................................................................................................................. 11
Write Transactions ................................................................................................................................................ 11
Posted Write Transactions .................................................................................................................................... 11
Memory Write and Invalidate Transactions .......................................................................................................... 12
Delayed Write Transactions .................................................................................................................................. 12
Write Transaction Address Boundaries ................................................................................................................ 13
Buffering Multiple Write Transactions .................................................................................................................. 13
Fast Back-to-Back Write Transactions .................................................................................................................. 13
Read Transactions ................................................................................................................................................. 14
Prefetchable Read Transactions ............................................................................................................................ 14
Non-prefetchable Read Transactions .................................................................................................................... 14
Read Pre-fetch Address Boundaries ...................................................................................................................... 14
Delayed Read Requests ......................................................................................................................................... 15
Delayed Read Completion with Target .................................................................................................................. 15
Delayed Read Completion on Initiator Bus ........................................................................................................... 15
Configuration Transactions ................................................................................................................................... 16
Type 0 Access to PI7C7100 ................................................................................................................................... 16
Type 1 to Type 0 Conversion ................................................................................................................................ 17
Type 1 to Type 1 Forwarding ................................................................................................................................ 18
Special Cycles ........................................................................................................................................................ 19
Transaction Termination ........................................................................................................................................ 19
Master Termination Initiated by PI7C7100 ............................................................................................................ 20
Master Abort Received by PI7C7100 ..................................................................................................................... 20
Target Termination Received by PI7C7100 ............................................................................................................ 21
Target Termination Initiated by PI7C7100 ............................................................................................................. 23
iii
05/08/00
ADVANCE INFORMATION
65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI7C7100
3-Port PCI Bridge
5.
5.1
5.2
5.2.1
5.2.2
5.3
5.3.1
5.3.2
5.4
5.4.1
5.4.2
6.
6.1
6.2
6.3
6.4
7.
7.1
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.3
7.4
8.
8.1
8.2
8.3
9.
9.1
9.2
9.2.1
9.2.2
9.2.3
10.
10.1
10.2
11.
11.1
11.2
11.3
12.
12.1
12.2
13.
13.1
13.2
Address Decoding
.................................................................................................................................................. 25
Address Ranges ..................................................................................................................................................... 25
I/O Address Decoding ........................................................................................................................................... 25
I/O Base and Limit Address Registers ................................................................................................................... 25
ISA Mode ............................................................................................................................................................... 26
Memory Address Decoding ................................................................................................................................... 26
Memory-Mapped I/O Base and Limit Address Registers ...................................................................................... 26
Prefetchable Memory Base and Limit Address Registers ...................................................................................... 27
VGA Support .......................................................................................................................................................... 28
VGA Mode ............................................................................................................................................................. 28
VGA Snoop Mode .................................................................................................................................................. 28
Transaction Ordering
........................................................................................................................................... 29
Transactions Governed by Ordering Rules ........................................................................................................... 29
General Ordering Guidelines .................................................................................................................................. 29
Ordering Rules ....................................................................................................................................................... 30
Data Synchronization ............................................................................................................................................. 31
Error Handling
...................................................................................................................................................... 32
Address Parity Errors ............................................................................................................................................. 32
Data Parity Errors ................................................................................................................................................... 32
Configuration Write Transactions to Configuration Space ................................................................................... 32
Read Transactions ................................................................................................................................................. 33
Delayed Write Transactions .................................................................................................................................. 33
Posted Write Transactions .................................................................................................................................... 35
Data Parity Error Reporting Summary .................................................................................................................... 36
System Error (SERR#) Reporting ........................................................................................................................... 42
Exclusive Access
................................................................................................................................................... 43
Concurrent Locks ................................................................................................................................................... 43
Acquiring Exclusive Access across PI7C7100 ....................................................................................................... 43
Ending Exclusive Access ....................................................................................................................................... 44
PCI Bus Arbitration
.............................................................................................................................................. 45
Primary PCI Bus Arbitration ................................................................................................................................... 45
Secondary PCI Bus Arbitration ............................................................................................................................. 45
Secondary Bus Arbitration Using the Internal Arbiter .......................................................................................... 45
Secondary Bus Arbitration Using an External Arbiter ........................................................................................... 46
Bus Parking ............................................................................................................................................................ 46
Clocks
.................................................................................................................................................................... 47
Primary Clock Inputs .............................................................................................................................................. 47
Secondary Clock Outputs ...................................................................................................................................... 47
Reset
...................................................................................................................................................................... 48
Primary Interface Reset .......................................................................................................................................... 48
Secondary Interface Reset ..................................................................................................................................... 48
Chip Reset .............................................................................................................................................................. 48
Supported Commands
............................................................................................................................................ 49
Primary Interface .................................................................................................................................................... 49
Secondary Interface ............................................................................................................................................... 51
Configuration Registers
....................................................................................................................................... 52
Config Register 1 .................................................................................................................................................... 52
Config Register 2 .................................................................................................................................................... 53
iv
05/08/00
ADVANCE INFORMATION
765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI7C7100
3-Port PCI Bridge
13.2.1
13.2.2
13.2.3
13.2.4
13.2.5
13.2.6
13.2.7
13.2.8
13.2.9
13.2.10
13.2.11
13.2.12
13.2.13
13.2.14
13.2.15
13.2.16
13.2.17
13.2.18
13.2.19
13.2.20
13.2.21
13.2.22
13.2.23
13.2.24
13.2.25
13.2.26
13.2.27
13.2.28
13.2.29
13.2.30
13.2.31
13.2.32
13.2.33
13.2.34
13.2.35
13.2.36
13.2.37
13.2.38
13.2.39
13.2.40
13.2.41
13.2.42
13.2.43
13.2.44
13.2.45
13.2.46
13.2.47
13.2.48
13.2.49
13.2.50
Config Register 1 or 2:Vendor ID Register (read only, bit 15-0; offset 00h) .......................................................... 54
Config Register 1: Device ID Register (read only, bit 31-16; offset 00h) ............................................................... 54
Config Register 2: Device ID Register (read only, bit 31-16; offset 00h) ............................................................... 54
Config Register 1: Command Register (bit 15-0; offset 04h) .................................................................................. 54
Config Register 2: Command Register (bit 15-0; offset 04h) .................................................................................. 55
Config Register 1 or 2: Status Register (for primary bus, bit 31-16; offset 04h) ..................................................... 56
Config Register 1 or 2: Revision ID Register (read only, bit 7-0; offset 08h) ......................................................... 57
Config Register 1 or 2: Class Code Register (read only, bit 31-8; offset 08h) ........................................................ 57
Config Register 1 or 2: Cache Line Size Register (read/write, bit 7-0; offset 0Ch) ................................................. 57
Config Register 1: Primary Latency Timer Register (read/write, bit 15-8; offset 0Ch) ............................................ 57
Config Register 2: Primary Latency Timer Register (read/write, bit 15-8; offset 0Ch) ............................................ 57
Config Register 1: Header Type Register (read only, bit 23-16; offset 0Ch) .......................................................... 57
Config Register 2: Header Type Register (read only, bit 23-16; offset 0Ch) .......................................................... 57
Config Register 1: Primary Bus Number Register (read/write, bit 7-0; offset 18h) ................................................. 57
Config Register 2: Primary Bus Number Register (read/write, bit 7-0; offset 18h) ................................................. 57
Config Register 1 or 2: Secondary Bus Number Register (read/write, bit 15-8; offset 18h) ................................... 57
Config Register 1 or 2: Subordinate Bus Number Register (read/write, bit 23-16; offset 18h) ............................... 57
Config Register 1 or 2: Secondary Latency Timer (read/write, bit 31-24; offset 18h) ............................................ 57
Config Register 1 or 2: I/O Base Register (read/write, bit 7-0; offset 1Ch) ............................................................ 57
Config Register 1 or 2: I/O Limit Register (read/write, bit 15-8; offset 1Ch) ........................................................... 57
Config Register 1 or 2: Secondary Status Register (bit 31-16; offset 1Ch) ............................................................ 58
Config Register 1 or 2: Memory Base Register (read/write, bit 15-0; offset 20h) ................................................... 59
Config Register 1 or 2: Memory Limit Register (read/write, bit 31:16; offset 20h) ................................................. 59
Config Register 1 or 2: Prefetchable Memory Base Register (read/write, bit 15-0;offset 24h) ............................... 59
Config Register 1 or 2: Prefetchable Memory Limit Register (read/write, bit 31-16; offset 24h) ............................ 59
Config Register 1 or 2: I/O Base Address Upper 16 Bits Register (read/write, bit 15-0; offset 30h) ...................... 59
Config Register 1 or 2: I/O Limit Address Upper 16 Bits Register (read/write, bit 31-16; offset 30h) .................... 59
Config Register 1 or 2: Subsystem Vendor ID (read/write, bit 15-0; offset 34h) .................................................... 59
Config Register 1 or 2: Subsystem ID (read/write, bit 31-16; offset 34h) ............................................................... 59
Config Register 1 or 2: Interrupt Pin Register (read only, bit 15-8; offset 3Ch) ..................................................... 59
Config Register 1 or 2: Bridge Control Register (bit 31-16; offset 3Ch) ................................................................. 60
Config Register 1 or 2: Diagnostic/Chip Control Register (bit 15-0; offset 40h) .................................................... 61
Config Register 1 or 2: Arbiter Control Register (bit 31-16; offset 40h) ................................................................. 61
Config Register 1: Primary Prefetchable Memory Base Register (Read/Write, bit 15-0; offset 44h) ..................... 62
Config Register 2: Primary Prefetchable Memory Base Register (Read/Write, bit 15-0; offset 44h) ..................... 62
Config Register 1: Primary Prefetchable Memory Limit Register (Read/Write, bit 31-16; offset 44h) .................... 62
Config Register 2: Primary Prefetchable Memory Limit Register (Read/Write, bit 31-16; offset 44h) .................... 62
Config Register 1 or 2: P_SERR# Event Disable Register (bit 7-0; offset 64h) ...................................................... 62
Config Register 1: Secondary Clock Control Register (bit 15-0; offset 68h) .......................................................... 63
Config Register 2: Secondary Clock Control Register (bit 15-0; offset 68h) .......................................................... 63
Config Register 1 or 2: Non-Posted Memory Base Register (read/write, bit 15-0; offset 70h) .............................. 64
Config Register 1 or 2: Non-Posted Memory Limit Register (read/write, bit 31-16; offset 70h) ............................. 64
Config Register 1: Port Option Register (bit 15-0; offset 74h) ............................................................................... 64
Config Register 2: Port Option Register (bit 15-0; offset 74h) ............................................................................... 65
Config Register 1 or 2: Master Timeout Counter Register (read/write, bit 31-16; offset 74h) ................................ 66
Config Register 1 or 2: Retry Counter Register (read/write, bit 31-0; offset 78h) .................................................. 66
Config Register 1 or 2: Sampling Timer Register (read/write, bit 31-0; offset 7Ch) ................................................ 66
Config Register 1 or 2: Successful I/O Read Count Register (read/write, bit 31-0; offset 80h) ............................. 66
Config Register 1 or 2: Successful I/O Write Count Register (read/write, bit 31-0; offset 84h) ............................. 66
Config Register 1 or 2: Successful Memory Read Count Register (read/write, bit 31-0; offset 88h) ..................... 66
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05/08/00
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