SwitchStar
TM
ATM Cell Based
8 x 8 1.2Gbps non-blocking
Integrated Switching Memory
Features List
Single chip supports an 8 x 8 port switch at 155Mbps per
port
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Central Memory Architecture eliminates Head-of-Line
Blocking by sharing the memory array with all ports
!
Low power dissipation
– 330mW (typ.)
!
Data Path Interface (DPI) provides configurable Input and
Output ports; up to 8 receive and 8 transmit ports at
155Mbps
!
Supports data rates up to 1.2Gbps with a 32-bit wide port
configuration; 155Mbps per 4-bit port
!
Can be cascaded for larger switch configurations
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Fast Input/Output port cycle times
!
Expander and Concentrator function is fully supported by
the Input and Output port configuration options
!
8192 cells (52 to 56 bytes each) of on-chip buffer memory
capacity
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IDT77V400
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Configurable cell lengths of 52, 53, 54, 55, or 56 bytes can
be independently chosen for Input and Output ports
Byte Addition or Byte Subtraction for x4/x8 to x16/x32
conversion capability
Internal header Cyclical Redundancy Check (CRC) and
generation logic on-chip
Header modification, pre-pend, and post-pend operations
available as well as Multicasting and Broadcasting
capability
High-bandwidth control port for queue controller system
block, up to 36 MHz cycle time
Can be used with the companion IDT77V500 Switch
Controller or custom logic for traffic management
Industrial temperature range (-40°C to +85°C) is available
Single +3.3V ± 300mV power supply
Available in an 208-pin Plastic Quad Flat Pack (PQFP) and
256-ball BGA
Block Diagram
External Interface
for Global Setup
and Control
8-bit Processor/
Call Setup
Manager
or IDT77V550
Data
Control
IDT77V500
Switch
Controller
Data
Control
155Mbps
PHY
Port 0
Port 0
155Mbps
PHY
,
IDT77V400
Switching
Memory
155Mbps
PHY
Port 7
Port 7
155Mbps
PHY
3606 drw 01
Figure 1 Typical 8x8 Switch Configuration using the IDT77V400 Switching Memory
SwitchStar and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
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2001 Integrated Device Technology, Inc.
March 31, 2001
DSC 3606/6
IDT77V400
Description
The IDT77V400 ATM Cell Based Switching Memory provides the
logic and memory necessary to perform high-speed buffering and
switching operations on ATM cell data. A single IDT77V400 provides a
cost effective switching element to implement an 8 x 8 155Mbps switch
with 1.2Gbps total switching bandwidth. The user configurable data
ports provide an aggregate bandwidth of 1.2Gbps for both receive and
transmit functions, and the cell lengths are user programmable to up to
56 bytes.
The memory provides storage for 8192 ATM cells, each of which can
be as large as 56-bytes in length. The main cell memory is implemented
as a Buffer Memory array, and an on-chip cell address counter keeps
track of cell refresh requirements. There are also sixteen double-buff-
ered Serial Access Memories (SAM); eight for receiving and eight for
transmitting the ATM cells.
The input data ports and output data ports are configurable from
eight ports of 4-bits at 155Mbps each up to one 32-bit wide port at
1.2Gbps. The sixteen data ports are asynchronous with respect to each
other, and each port provides an independent data clock and cell
framing signal for start of cell indication. The SAMs are double-buffered
for each input and each output port to allow one cell to be transferred to
or from the internal memory while that data port continues to receive or
transmit a second cell. The cell framing and data clock signals imple-
ment a simple handshaking and synchronization protocol which allows
multiple Switching Memories to be connected to construct larger switch
arrays without requiring additional hardware.
The control interface of the IDT77V400 includes a 6-bit Command
Bus (CMD0-5), a 32-bit Control Data Bus (IOD0-31), a Chip Select pin
(CS), a 4-bit Address field (ADDR0-3), a RESET pin, an Output Enable
pin (OE), a Control Enable pin (CTLEN) and a CRCERR pin. All control
operations are synchronized with respect to the System Clock (SCLK),
with the exception of RESET, CTLEN, and OE, which are fully asynchro-
nous.
The internal configuration register of the IDT77V400 can be
accessed through the Control Data Bus to define the cell length and the
input and output data port configurations. Internal error and status regis-
ters contain status information regarding each SAM and are accessible
via the Control Data Bus (IOD0-31). Input SAM full or Output SAM
empty status for all SAMs may be obtained in one access operation.
Additional information regarding the reception of short or long cells and
Input SAM overflow may also be obtained through the Control Data Bus.
The command set of the Switching Memory provides functions for
storing cells in the shared memory, loading Output SAMs, polling the
status of the data ports, retrieving and storing original or modified
header bytes and pre-pend or post-pend bytes, and refreshing the cell
memory. Header CRC errors are indicated by a LOW CRCERR pin; the
CRC comparison byte may also be accessed via the status register,
which indicates the IPort on which the error was detected. A new CRC
can be generated upon storing a new header in the PHEC command.
Cell headers may be modified upon cell reception at the input ports or
upon cell transmit at the output ports. User defined pre-pend and post-
pend bytes may also be stored, retrieved, and modified through the
Control Data Bus.
The IDT77V400 has a generic control interface which supports a
variety of queuing disciplines. By maintaining the memory control in an
external controller, system level switching performance may be modified
over time as requirements change. In normal operation, the Switching
Memory port status is polled by the control function through the Control
Data Bus. Upon receiving a cell, the control function can retrieve the
header, check the CRC result, and store a new header if needed prior to
moving the cell to the shared memory. Pre-pended or post-pended
bytes may also be added or retrieved during this time. The output ports
are polled at the same time to determine when to send new cells to the
Output SAMs. The cell lengths of the input ports do not need to be the
same as the output port cell lengths, although all input ports and output
ports respectively must be configured to the same cell length.
Please refer to the SwichStar User Manual for additional feature
details and implementation information.
The IDT77V400 is fully 3.3V LVTTL compatible, and is packaged in
an 208-pin Plastic Quad Flatpack (PQFP) and a 256-ball BGA.
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March 31, 2001
PCB Design
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