GS8342S09AGE-200S datasheet, PDF

Datasheet> All Categories > storage> storage> GS8342S09AGE-200S

GS8342S09AGE-200S: DescriptionDDR SRAM, 4MX9, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, MO-216CAB-1, FPBGA-165; Categorystorage storage; File Size2MB，37 Pages; ManufacturerGSI Technology; Websitehttp://www.gsitechnology.com/; Environmental Compliance

Download Datasheet Parametric View All

GS8342S09AGE-200S Overview

DDR SRAM, 4MX9, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, MO-216CAB-1, FPBGA-165

GS8342S09AGE-200S Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	GSI Technology
Parts packaging code	BGA
package instruction	LBGA,
Contacts	165
Reach Compliance Code	compliant
ECCN code	3A991.B.2.B
Maximum access time	0.45 ns
Other features	PIPELINED ARCHITECTURE
JESD-30 code	R-PBGA-B165
JESD-609 code	e1
length	17 mm
memory density	37748736 bit
Memory IC Type	DDR SRAM
memory width	9
Humidity sensitivity level	3
Number of functions	1
Number of terminals	165
word count	4194304 words
character code	4000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	4MX9
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	1.5 mm
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN SILVER COPPER
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	15 mm

Preview

Download Datasheet

View All

Preliminary

GS8342S08/09/18/36AE-333/300/250/200/167

165-Bump BGA

Commercial Temp

Industrial Temp

Features

• Simultaneous Read and Write SigmaSIO™ Interface

• JEDEC-standard pinout and package

• Dual Double Data Rate interface

• Byte Write (x36, x18, and x9) and Nybble Write (x8) function

• DLL circuitry for wide output data valid window and future

frequency scaling

• Burst of 2 Read and Write

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation

• Fully coherent read and write pipelines

• ZQ mode pin for programmable output drive strength

• IEEE 1149.1 JTAG-compliant Boundary Scan

• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

• Pin-compatible with future 72Mb and 144Mb devices

36Mb Burst of 2

DDR SigmaSIO-II SRAM

167 MHz–333 MHz

1.8 V V

1.8 V and 1.5 V I/O

Bottom View

165-Bump, 15 mm x 17 mm BGA

1 mm Bump Pitch, 11 x 15 Bump Array

JEDEC Std. MO-216, Variation CAB-1

SigmaRAM™ Family Overview

GS8342S08/09/18/36AE are built in compliance with the

SigmaSIO-II SRAM pinout standard for Separate I/O

synchronous SRAMs. They are 37,748,736-bit (36Mb)

SRAMs. These are the first in a family of wide, very low

voltage HSTL I/O SRAMs designed to operate at the speeds

needed to implement economical high performance

networking systems.

Clocking and Addressing Schemes

A Burst of 2 SigmaSIO-II SRAM is a synchronous device. It

employs dual input register clock inputs, K and K. The device

also allows the user to manipulate the output register clock

input quasi independently with dual output register clock

inputs, C and C. If the C clocks are tied high, the K clocks are

routed internally to fire the output registers instead. Each Burst

of 2 SigmaSIO-II SRAM also supplies Echo Clock outputs,

CQ and CQ, which are synchronized with read data output.

When used in a source synchronous clocking scheme, the Echo

Clock outputs can be used to fire input registers at the data’s

destination.

Because Separate I/O Burst of 2 RAMs always transfer data in

two packets, A0 is internally set to 0 for the first read or write

transfer, and automatically incremented by 1 for the next

transfer. Because the LSB is tied off internally, the address

field of a Burst of 2 RAM is always one address pin less than

the advertised index depth (e.g., the 2M x 18 has a 1M

addressable index).

Parameter Synopsis

- 333

tKHKH

tKHQV

3.0 ns

0.45 ns

-300

3.3 ns

0.45 ns

-250

4.0 ns

0.45 ns

-200

5.0 ns

0.45 ns

-167

6.0 ns

0.5 ns

Rev: 1.00 6/2006

1/37

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Recommended Resources

RC coupled self-excited multivibrator circuit

Motorcycle brake light delay turn-off circuit

Wind battery charger

Photoelectric switch determines the shape control circuit of transmission belt products

"clairvoyance" charger (6v battery multi-function charger circuit)

Quartz crystal sine oscillator circuit

TI's power management solutions for consumer electronics: [b][size=4]Brief description: Texas Instruments (TI) power management IC has a variety of solutions. Among them, TPS65053x is an integrated power management IC for applications that are powered by a s...; qwqwqw2088 Analogue and Mixed Signal

Can anyone find the manual for this component?: Which manufacturer is this? Why does it look so familiar? But I can't remember it. Please help....; 小太阳yy Analog electronics

My experience in buying electronic components: Today I was free and had the urge to write something. What should I write? I started to learn electronic technology in my junior year, starting with the 51 single-chip microcomputer, and climbed up st...; proan Buy&Sell

Can high-end fingerprint locks promote the development of access control systems?: As a derivative product of access control identification, fingerprint locks rely on the development of biometric technology. They have gradually emerged and entered more families abroad. For our domes...; anfangtd Industrial Control Electronics

So that's why the express delivery for Double Eleven has not arrived yet: [color=#333333][font=Arial,]Finally figured out why the Double Eleven delivery hasn’t arrived yet[/font][/color]{:1_101:}[font=Arial, Microsoft YaHei][color=#333333][size=12px] [/size][/color][/font]...; qwqwqw2088 Talking

COM port resource release: I am working on a dial-up program. After a long period of dialing (while doing data services), I found that the dial-up was unsuccessful. The error code returned was that the COM port was occupied by ...; rainchencxy Embedded System

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components