PRELIMINARY
a+
DS32501/DS32502/DS32503/DS32504
Single-/Dual-/Triple-/Quad-Port
DS3/E3/STS-1 LIUs
www.maxim-ic.com
GENERAL DESCRIPTION
The DS32501 (single), DS32502 (dual), DS32503
(triple), and DS32504 (quad) line interface units
(LIUs) are highly integrated, low-power, feature-rich
LIUs for DS3, E3, and STS-1 applications. Each LIU
port in these devices has independent receive and
transmit paths, a jitter attenuator, a full-featured
pattern generator and detector, performance
monitoring counters, and a complete set of
loopbacks. An on-chip clock adapter generates all
line-rate clocks from a single input clock. Ports are
independently software configurable for DS3, E3, and
STS-1 and can be individually powered down.
Control interface options include 8-bit parallel, SPI,
and hardware mode.
FEATURES
Pin-Compatible Family of Products
Each Port Independently Configurable
Receive Clock and Data Recovery for Up to
457 meters (1500 feet) of 75Ω Coaxial Cable
Standards-Compliant Transmit Waveshaping
Uses 1:1 Transformers on Both Tx and Rx
Three Control Interface Options: 8/16-Bit
Parallel, SPI, and Hardware Mode
Jitter Attenuators (One Per Port) Can be
Placed in the Receive Path or the Transmit
Path
Jitter Attenuators Have Provisionable Buffer
Depth: 16, 32, 64, or 128 Bits
Built-In Clock Adapter Generates All Line-
Rate Clocks from a Single Input Clock (DS3,
E3, STS-1, 12.8MHz, 19.44MHz, 38.88MHz,
77.76MHz)
Per-Port Programmable Internal Line
Termination Requiring Only External
Transformers
High-Impedance Tx and Rx, Even When
V
DD
= 0, Enables Hot-Swappable, 1:1, and 1+1
Board Redundancy Without Relays
Per-Port BERT for PRBS and Repetitive
Pattern Generation and Detection
Tx and Rx Open- and Short-Detection
Circuitry
Transmit Driver Monitor Circuitry
Receive Loss-of-Signal (LOS) Monitoring
Compliant with ANSI T1.231 and ITU G.775
Automatic Data Squelching on Receive LOS
Large Line Code Performance Monitoring
Counters for Accumulation Intervals Up to 1s
Local and Remote Loopbacks
Transmit Common Clock Option
Power-Down Capability for Unused Ports
Low-Power 1.8V/3.3V Operation (5V Tolerant
I/O)
Industrial Temperature Range: -40°C to +85°C
Small Package: (13mm)
2
144-Pin TE-CSBGA
IEEE 1149.1 JTAG Support
APPLICATIONS
SONET/SDH and PDH
Multiplexers
ATM and Frame Relay
Equipment
WAN Routers and
Switches
Digital Cross-Connects
Access Concentrators
PBXs
DSLAMs
CSU/DSUs
ORDERING INFORMATION
PART
DS32501*
DS32501N*
DS32502*
DS32502N*
DS32503*
DS32503N*
DS32504*
DS32504N*
LIUs
1
1
2
2
3
3
4
4
TEMP RANGE
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
PIN-PACKAGE
144 TE-CSBGA
144 TE-CSBGA
144 TE-CSBGA
144 TE-CSBGA
144 TE-CSBGA
144 TE-CSBGA
144 TE-CSBGA
144 TE-CSBGA
Note:
Add “+” for the lead-free package option.
*Future
product—contact factory for availability.
Functional Diagram appears in Section
3
(see
Figure 3-1).
Note:
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here:
www.maxim-ic.com/errata.
1 of 124
REV: 042007
PRELIMINARY
TABLE OF CONTENTS
1.
2.
3.
4.
5.
6.
DS32501/DS32502/DS32503/DS32504
ACRONYMS .........................................................................................................................6
STANDARDS COMPLIANCE...............................................................................................7
DETAILED DESCRIPTION ...................................................................................................8
APPLICATION EXAMPLE..................................................................................................10
BLOCK DIAGRAM .............................................................................................................11
FEATURE DETAILS ...........................................................................................................12
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
G
LOBAL
F
EATURES
.......................................................................................................................12
R
ECEIVER
F
EATURES
....................................................................................................................12
T
RANSMITTER
F
EATURES
..............................................................................................................12
J
ITTER
A
TTENUATOR
F
EATURES
....................................................................................................12
B
IT
E
RROR
R
ATE
T
ESTER
(BERT) F
EATURES
................................................................................13
C
LOCK
A
DAPTER
F
EATURES
..........................................................................................................13
P
ARALLEL
M
ICROPROCESSOR
I
NTERFACE
F
EATURES
.....................................................................13
SPI S
ERIAL
M
ICROPROCESSOR
I
NTERFACE
F
EATURES
..................................................................13
M
ISCELLANEOUS
F
EATURES
..........................................................................................................13
T
EST
F
EATURES
............................................................................................................................13
L
OOPBACK
F
EATURES
...................................................................................................................13
7.
8.
CONTROL INTERFACE MODES .......................................................................................14
PIN DESCRIPTIONS ..........................................................................................................15
8.1
8.2
S
HORT
P
IN
D
ESCRIPTIONS
............................................................................................................15
D
ETAILED
P
IN
D
ESCRIPTIONS
........................................................................................................17
LIU M
ODE
....................................................................................................................................23
T
RANSMITTER
...............................................................................................................................23
Transmit Clock .................................................................................................................................... 23
Framer Interface Format and the B3ZS/HDB3 Encoder..................................................................... 23
Error Insertion ..................................................................................................................................... 24
AIS Generation.................................................................................................................................... 24
Waveshaping ...................................................................................................................................... 24
Line Build-Out ..................................................................................................................................... 27
Line Driver........................................................................................................................................... 28
Interfacing to the Line ......................................................................................................................... 28
Driver Monitor and Output Failure Detection ...................................................................................... 28
Power-Down........................................................................................................................................ 28
Jitter Generation (Intrinsic).................................................................................................................. 28
Jitter Transfer ...................................................................................................................................... 29
Interfacing to the Line ......................................................................................................................... 29
Optional Preamp ................................................................................................................................. 29
Automatic Gain Control (AGC) and Adaptive Equalizer ..................................................................... 30
Clock and Data Recovery (CDR) ........................................................................................................ 30
Loss-of-Signal (LOS) Detector............................................................................................................ 30
Framer Interface Format and the B3ZS/HDB3 Decoder .................................................................... 31
Power-Down........................................................................................................................................ 32
Input Failure Detection........................................................................................................................ 32
Jitter and Wander Tolerance............................................................................................................... 33
Jitter Transfer ...................................................................................................................................... 34
9.
FUNCTIONAL DESCRIPTION............................................................................................23
9.1
9.2
9.2.1
9.2.2
9.2.3
9.2.4
9.2.5
9.2.6
9.2.7
9.2.8
9.2.9
9.2.10
9.2.11
9.2.12
9.3
R
ECEIVER
.....................................................................................................................................29
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
9.3.7
9.3.8
9.3.9
9.3.10
9.4
J
ITTER
A
TTENUATOR
.....................................................................................................................35
2 of 124
PRELIMINARY
9.5
9.5.1
9.5.2
9.5.3
DS32501/DS32502/DS32503/DS32504
BERT...........................................................................................................................................36
Configuration and Monitoring.............................................................................................................. 36
Receive Pattern Detection .................................................................................................................. 37
Transmit Pattern Generation............................................................................................................... 39
9.6
9.7
L
OOPBACKS
..................................................................................................................................40
G
LOBAL
R
ESOURCES
....................................................................................................................40
Clock Rate Adapter (CLAD)................................................................................................................ 40
One-Second Reference Generator ..................................................................................................... 42
General-Purpose I/O Pins................................................................................................................... 42
Performance Monitor Register Update ............................................................................................... 43
Transmit Manual Error Insertion ......................................................................................................... 43
8-Bit and 16-Bit Bus Widths ................................................................................................................ 44
Byte Swap Mode ................................................................................................................................. 44
Read-Write and Data Strobe Modes................................................................................................... 44
Multiplexed and Nonmultiplexed Operation ........................................................................................ 44
Clear-On-Read and Clear-On-Write Modes ....................................................................................... 44
Global Write Mode .............................................................................................................................. 44
9.7.1
9.7.2
9.7.3
9.7.4
9.7.5
9.8
8-/16-B
IT
P
ARALLEL
M
ICROPROCESSOR
I
NTERFACE
......................................................................44
9.8.1
9.8.2
9.8.3
9.8.4
9.8.5
9.8.6
9.9 SPI S
ERIAL
M
ICROPROCESSOR
I
NTERFACE
...................................................................................45
9.10 I
NTERRUPT
S
TRUCTURE
................................................................................................................47
9.11 R
ESET AND
P
OWER
-D
OWN
............................................................................................................48
10. REGISTER MAPS AND DESCRIPTIONS ..........................................................................50
10.1 O
VERVIEW
....................................................................................................................................50
10.1.1 Status Bits ........................................................................................................................................... 50
10.1.2 Configuration Fields ............................................................................................................................ 50
10.1.3 Counters.............................................................................................................................................. 50
10.2
10.3
10.4
10.5
10.6
10.7
10.8
O
VERALL
R
EGISTER
M
AP
..............................................................................................................51
G
LOBAL
R
EGISTERS
......................................................................................................................52
P
ORT
C
OMMON
R
EGISTERS
..........................................................................................................60
LIU R
EGISTERS
............................................................................................................................68
B3ZS/HDB3 E
NCODER
R
EGISTERS
..............................................................................................77
B3ZS/HDB3 D
ECODER
R
EGISTERS
..............................................................................................79
BERT R
EGISTERS
........................................................................................................................84
11. JTAG INFORMATION ........................................................................................................93
12. ELECTRICAL CHARACTERISTICS ..................................................................................94
13. PIN ASSIGNMENTS .........................................................................................................108
14. PACKAGE INFORMATION ..............................................................................................121
14.1 13
MM X
13
MM
144-L
EAD
TE-CSBGA (56-G6016-001) ................................................................121
15. THERMAL INFORMATION...............................................................................................122
16. TRADEMARK ACKNOWLEDGEMENTS .........................................................................123
17. DATA SHEET REVISION HISTORY ................................................................................124
3 of 124
PRELIMINARY
LIST OF FIGURES
DS32501/DS32502/DS32503/DS32504
Figure 3-1. Functional Diagram ................................................................................................................................... 8
Figure 3-2. External Connections, Internal Termination Enabled................................................................................ 8
Figure 3-3. External Connections, Internal Termination Disabled............................................................................... 9
Figure 4-1. 3-Port Unchannelized DS3/E3 Card ....................................................................................................... 10
Figure 5-1. Block Diagram ......................................................................................................................................... 11
Figure 9-1. DS3 Waveform Template ........................................................................................................................ 25
Figure 9-2. STS-1 Waveform Template..................................................................................................................... 26
Figure 9-3. E3 Waveform Template........................................................................................................................... 27
Figure 9-4. STS-1 and E3 Jitter Tolerance................................................................................................................ 33
Figure 9-5. DS3 Jitter Tolerance................................................................................................................................ 34
Figure 9-6. DS3 and E3 Wander Tolerance .............................................................................................................. 34
Figure 9-7. Jitter Attenuation/Jitter Transfer .............................................................................................................. 35
Figure 9-8. PRBS Synchronization State Diagram.................................................................................................... 38
Figure 9-9. Repetitive Pattern Synchronization State Diagram................................................................................. 39
Figure 9-10. SPI Clock Polarity and Phase Options.................................................................................................. 46
Figure 9-11. SPI Bus Transactions............................................................................................................................ 46
Figure 9-12. Interrupt Signal Flow ............................................................................................................................. 47
Figure 12-1. Transmitter Framer Interface Timing Diagram...................................................................................... 97
Figure 12-2. Receiver Framer Interface Timing Diagram .......................................................................................... 97
Figure 12-3. Parallel CPU Interface Intel Read Timing Diagram (Nonmultiplexed) ................................................ 101
Figure 12-4. Parallel CPU Interface Intel Write Timing Diagram (Nonmultiplexed) ................................................ 101
Figure 12-5. Parallel CPU Interface Motorola Read Timing Diagram (Nonmultiplexed) ......................................... 102
Figure 12-6. Parallel CPU Interface Motorola Write Timing Diagram (Nonmultiplexed) ......................................... 102
Figure 12-7. Parallel CPU Interface Intel Read Timing Diagram (Multiplexed) ....................................................... 103
Figure 12-8. Parallel CPU Interface Intel Write Timing Diagram (Multiplexed) ....................................................... 103
Figure 12-9. Parallel CPU Interface Motorola Read Timing Diagram (Multiplexed)................................................ 104
Figure 12-10. Parallel CPU Interface Motorola Write Timing Diagram (Multiplexed).............................................. 104
Figure 12-11. SPI Interface Timing Diagram ........................................................................................................... 106
Figure 12-12. JTAG Timing Diagram....................................................................................................................... 107
Figure 13-1. DS32504 Pin Assignment—Microprocessor Interface Mode.............................................................. 109
Figure 13-2. DS32504 Pin Assignment—SPI Interface Mode................................................................................. 110
Figure 13-3. DS32504 Pin Assignment—Hardware Mode ...................................................................................... 111
Figure 13-4. DS32503 Pin Assignment—Microprocessor Interface Mode.............................................................. 112
Figure 13-5. DS32503 Pin Assignment—SPI Interface Mode................................................................................. 113
Figure 13-6. DS32503 Pin Assignment—Hardware Mode ...................................................................................... 114
Figure 13-7. DS32502 Pin Assignment—Microprocessor Interface Mode.............................................................. 115
Figure 13-8. DS32502 Pin Assignment—SPI Interface Mode................................................................................. 116
Figure 13-9. DS32502 Pin Assignment—Hardware Mode ...................................................................................... 117
Figure 13-10. DS32501 Pin Assignment—Microprocessor Interface Mode............................................................ 118
Figure 13-11. DS32501 Pin Assignment—SPI Interface Mode............................................................................... 119
Figure 13-12. DS32501 Pin Assignment—Hardware Mode.................................................................................... 120
4 of 124
PRELIMINARY
LIST OF TABLES
DS32501/DS32502/DS32503/DS32504
Table 2-1. Applicable Telecommunications Standards ............................................................................................... 7
Table 8-1. Short Pin Descriptions .............................................................................................................................. 15
Table 8-2. Analog Line Interface Pin Descriptions .................................................................................................... 17
Table 8-3. Digital Framer Interface Pin Descriptions................................................................................................. 17
Table 8-4. Global Pin Descriptions ............................................................................................................................ 18
Table 8-5. Hardware Interface Pin Descriptions........................................................................................................ 18
Table 8-6. Parallel Interface Pin Descriptions ........................................................................................................... 20
Table 8-7. SPI Serial Interface Pin Descriptions ....................................................................................................... 21
Table 8-8. CLAD Pin Descriptions ............................................................................................................................. 21
Table 8-9. JTAG Pin Descriptions ............................................................................................................................. 22
Table 8-10. Power-Supply Pin Descriptions .............................................................................................................. 22
Table 8-11. Manufacturing Test Pin Descriptions...................................................................................................... 22
Table 9-1. DS3 Waveform Equations ........................................................................................................................ 25
Table 9-2. DS3 Waveform Test Parameters and Limits ............................................................................................ 25
Table 9-3. STS-1 Waveform Equations ..................................................................................................................... 26
Table 9-4. STS-1 Waveform Test Parameters and Limits......................................................................................... 26
Table 9-5. E3 Waveform Test Parameters and Limits............................................................................................... 27
Table 9-6. Jitter Generation ....................................................................................................................................... 28
Table 9-7. Transformer Characteristics ..................................................................................................................... 29
Table 9-8. Recommended Transformers................................................................................................................... 29
Table 9-9. Pseudorandom Pattern Generation.......................................................................................................... 36
Table 9-10. Repetitive Pattern Generation ................................................................................................................ 36
Table 9-11. CLAD Clock Source Settings ................................................................................................................. 41
Table 9-12. CLAD Clock Pin Output Settings............................................................................................................ 41
Table 9-13. Global One-Second Reference Source.................................................................................................. 42
Table 9-14. GPIO Pin Global Signal Assignments .................................................................................................... 42
Table 9-15. GPIO Pin Control.................................................................................................................................... 43
Table 9-16. Reset and Power-Down Sources ........................................................................................................... 48
Table 10-1. Overall Register Map.............................................................................................................................. 51
Table 10-2. Port Registers......................................................................................................................................... 51
Table 10-3. Global Register Map............................................................................................................................... 52
Table 10-4. Port Common Register Map................................................................................................................... 60
Table 10-5. LIU Register Map.................................................................................................................................... 68
Table 10-6. B3ZS/HDB3 Encoder Register Map ....................................................................................................... 77
Table 10-7. B3ZS/HDB3 Decoder Register Map....................................................................................................... 79
Table 10-8. BERT Register Map................................................................................................................................ 84
Table 11-1. JTAG ID Code ........................................................................................................................................ 93
Table 12-1. Recommended DC Operating Conditions .............................................................................................. 94
Table 12-2. DC Characteristics.................................................................................................................................. 95
Table 12-3. Framer Interface Timing ......................................................................................................................... 96
Table 12-4. Receiver Input Characteristics—DS3 and STS-1 Modes....................................................................... 98
Table 12-5. Receiver Input Characteristics—E3 Mode ............................................................................................. 98
Table 12-6. Transmitter Output Characteristics—DS3 and STS-1 Modes................................................................ 99
Table 12-7. Transmitter Output Characteristics—E3 Mode....................................................................................... 99
Table 12-8. Parallel CPU Interface Timing .............................................................................................................. 100
Table 12-9. SPI Interface Timing ............................................................................................................................. 105
Table 12-10. JTAG Interface Timing........................................................................................................................ 107
Table 13-1. Pin Assignments Sorted by Signal Name for DS32504 (Microprocessor Interface Mode).................. 108
Table 15-1. Thermal Properties—Natural Convection............................................................................................. 122
Table 15-2. Theta-JA (θ
JA
) vs. Airflow...................................................................................................................... 122
5 of 124
Embedded System
京公网安备 11010802033920号
EEWORLD
