DS1746_12 datasheet, PDF - EEWORLD Datasheet

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DS1746_12: DescriptionY2K-Compliant, Nonvolatile Timekeeping RAMs; File Size426KB，16 Pages; ManufacturerMaxim; Websitehttps://www.maximintegrated.com/en.html

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DS1746_12 Overview

Y2K-Compliant, Nonvolatile Timekeeping RAMs

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19-5503; Rev 3/12

DS1746/DS1746P

Y2K-Compliant, Nonvolatile Timekeeping RAMs

FEATURES



Integrated NV SRAM, Real-Time Clock,

Crystal, Power-Fail Control Circuit, and

Lithium Energy Source

Clock Registers are Accessed Identically to

the Static RAM. These Registers are Resident

in the Eight Top RAM Locations.

Century Byte Register (i.e., Y2K Compliant)

Totally Nonvolatile with Over 10 Years of

Operation in the Absence of Power

BCD-Coded Century, Year, Month, Date,

Day, Hours, Minutes, and Seconds with

Automatic Leap Year Compensation Valid

Up to the Year 2100

Battery Voltage-Level Indicator Flag

Power-Fail Write Protection Allows for ±10%

Power Supply Tolerance

Lithium Energy Source is Electrically

Disconnected to Retain Freshness Until

Power is Applied for the First Time

DIP Module Only

Standard JEDEC Byte-Wide 128k x 8 Static

RAM Pinout

PowerCap Module Board Only

Surface Mountable Package for Direct

Connection to PowerCap Containing

Battery and Crystal

Replaceable Battery (PowerCap)

Power-On Reset Output

Pin-for-Pin Compatible with Other Densities

of DS174xP Timekeeping RAM

Also Available in Industrial Temperature

Range: -40°C to +85°C

Underwriters Laboratories (UL) Recognized

PIN CONFIGURATIONS

TOP VIEW

N.C.

A16

A14

A12

DQ0

DQ1

DQ2

GND

Maxim

DS1746

A15

N.C.

A13

A11

A10

DQ7

DQ6

DQ5

DQ4

DQ3



Encapsulated DIP

N.C.

A15

A16

RST

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

GND

DS1746P

Maxim

GND

BAT

N.C.

A14

A13

A12

A11

A10



(Uses DS9034PCX+ or DS9034I-PCX+ PowerCap)

PowerCap Module Board

Note:

Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device

may be simultaneously available through various sales channels. For information about device errata, click here:

www.maxim-ic.com/errata.

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DS1746/DS1746P Y2K-Compliant, Nonvolatile Timekeeping RAMs

Figure 1. Block Diagram

The DS1746 is available in two packages (32-pin DIP and 34-pin PowerCap module). The 32-pin DIP

style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin

PowerCap Module Board is designed with contacts for connection to a separate PowerCap (DS9034PCX)

that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the

DS1746P after the completion of the surface mount process. Mounting the PowerCap after the surface

mount process prevents damage to the crystal and battery due to the high temperatures required for solder

reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module Board and PowerCap

are ordered separately and shipped in separate containers. The part number for the PowerCap is

DS9034PCX.

PACKAGES

CLOCK OPERATIONS—READING THE CLOCK

While the double-buffered register structure reduces the chance of reading incorrect data, internal updates

to the DS1746 clock registers should be halted before clock data is read to prevent reading of data in

transition. However, halting the internal clock register updating process does not affect clock accuracy.

Updating is halted when a one is written into the read bit, bit 6 of the century register (see Table 2). As

long as a one remains in that position, updating is halted. After a halt is issued, the registers reflect the

count, that is day, date, and time that was current at the moment the halt command was issued. However,

the internal clock registers of the double-buffered system continue to update so that the clock accuracy is

not affected by the access of data. All of the DS1746 registers are updated simultaneously after the

internal clock register updating process has been re-enabled. Updating is within a second after the read bit

is written to zero. The READ bit must be a zero for a minimum of 500µs to ensure the external registers

will be updated.

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