65510
Flat Panel VGA Controller
s
Highly integrated solution and small
s
Supports Dual Panel/Dual Drive
fast screen updates (internal asyn-
chronous 16-level FIFO)
s
Text Enhancement feature improves
form factor flat panel controller
solution
• Integrated 256x18 palette
• Direct support for Dual or Single
Scan panel
• Separate address and data buses
• Single clock source
• 100-pin package
s
Single 256Kx16 DRAM provides
(D/D) and Single Panel/Single Drive
(S/S) LCD, Plasma and El Panels
s
Generates 64 gray levels of
contrast of text on flat panel displays
s
Three software selectable RGB color
Monochrome panels
s
Single clock source with rate multi-
to gray scale reduction techniques
s
Full backwards compatibility with
plier function to generate a wide
range of clock frequencies
s
Optional "clock doubler" func-
EGA, CGA, MDA and Hercules
graphics standards
s
Chip pinouts optimized for PCB
two-chip VGA subsystem
s
Memory options are (1) 256Kx16
tionality
s
Programmable vertical compensa-
layout
s
Programmable polynomial based
DRAM or (4) 256Kx4 DRAMs
s
Mixed 3.3V/5.0V panel, bus and
tion techniques increase usable
display area
s
Intelligent SMARTMAP™ color to
Frame Rage Control gray scale
algorithm supports fast response
"mouse quick" displays by reducing
flicker without increasing panel
vertical refresh rate
s
16-bit display memory operations
memory interface capability for low
power operation
s
Advanced power management fea-
gray scale conversion
s
Fully compatible with IBM
®
VGA
s
High performance resulting from
tures minimize power consumption
during panel operation
s
Dedicated input pin supports mini-
buffered writes (Write Buffer) and
mum power operation in Suspend
and Resume modes
s
Register programmable 4mA or 8mA
S in g le C loc k S o u rc e
drive on all bus data line (D0-15) and
panel control and data signals
s
Multiple Bus Interface support for
B IO S
ROM
A d dress
D a ta
65510
C o n tr o l
P a n el C on trol
P an el D a ta
• High-speed x86 SL PI Bus
• High-speed x86 SX/DX Local Bus
• EISA/ISA (PC/AT) Bus
• Micro Channel (MC) Bus
s
High performance Linear Accelera-
IS A , M C , x 8 6 S L P I o r
x 8 6 S X /D X L oca l B u s
T o F la t
P a n el
D is p la y
25 6K x16
DRAM
tion™ drivers for Windows™
acceleration
System Block Diagram
PRELIMINARY
Product Overview
The 65510 VGA flat panel controller
provides a very low power consumption,
minimum chip-count, minimum-board
space, low-cost graphics solution for
inexpensive notebook, sub-notebook,
handheld and pen-based portable PCs and
word processors. The 65510 only
requires a single 256Kx16 DRAM and
single clock input, such that a complete
VGA subsystem can be implemented with
just two ICs.
The 65510 employs a variety of advanced
power management features to reduce
power consumption of the display
subsystem and extend battery life. The
65510's internal logic, memory interface,
bus interface and flat panel interface can
be independently configured to operate
at either 3.3V or 5V. The 65510 is opti-
mized for minimum power consumption
during normal operation and two power-
saving modes - Panel Off and Standby.
The 65510 supports a wide variety of
monochrome Single-Panel / Single Drive
(SS) and Dual-Panel / Dual Drive (DD)
STN LCDs, TFT LCDs EL and plasma
panels with up to 64 gray scales at
640x480 resolution or 16 gray scales at
800x600 resolution. The 65510 provides
a variety of programmable features to
optimize display quality, such as Vertical
and Horizontal Compensation, SMART-
MAP™ Text Enhancement, three select-
able color-to-gray scale reduction tech-
niques and a polynomial FRC grayscale
algorithm, which reduces flicker on fast-
response "mouse quick" LCD's without
No external buffers or glue logic are required for the 65510's bus interface, memory interface,
or panel interface.
increasing the LCD's vertical refresh rate.
The 65510 includes a number of perfor-
mance-enhancement techniques, which
provide good performance at low clock
frequencies (resulting in low power con-
sumption). The 65510's x86 SL PI and
x86 DX/SX local bus operation provides
high performance in 256-color modes.
The 65510's internal asynchronous FIFO
design provides minimum wait-state
reads and fast display updates. The
65510's linearly addressable video
memory allows the CPU to linearly
address the 512 KBytes of video memory,
enabling the use of high-performance
32-bit software drivers (called Linear
Acceleration).
The 65510 is fully compatible with the
VGA graphics standard at the register,
gate, and BIOS levels. The 65510 pro-
vides full backwards compatibility with
the EGA, CGA, MDA and Hercules
graphics standards without using NMIs.
CHIPS' and third-party vendors supply
fully VGA-compatible BIOS's, end-user
utilities and drivers for common applica-
tion programs (e.g., Windows, OS/2,
WordPerfect, Lotus, etc.). CHIPS'
drivers for Windows include a Big
Cursor (to increase the cursor's legibility
on monochrome flat panels) and 32-bit
Linear Acceleration and panning/scroll-
ing drivers (to increase performance).
For more information contact your local
sales representative.
Copyright 1995, Chips and Technologies, Inc. ALL RIGHTS RESERVED.
CHIPS Logo, CHIPSlink, CHIPSPort, ELEAT, LeAPSet, NEAT, NEATsx, PEAK, PRINTGINE,
SCAT, SuperMathDX, SuperState and WINGINE are registered trademarks of Chips and Tech-
nologies, Inc.
CHIPSet, WinPC, and XRAM Video Cache are trademarks of Chips and Technologies, Inc.
All other trademarks are the property of their respective holders.
MINIMUM CHIP COUNT / BOARD SPACE
The 65510 provides a minimum chip count / board space, low-cost VGA sub-system. The
65510 integrates a versatile VGA flat panel controller and 256x18 VGA palette in a 100-pin
plastic flat pack package. The 65510 requires a single 256Kx16 DRAM and single clock input,
such that a complete VGA sub-system for motherboard applications can be implemented with
just two ICs:
Qty
1
1
2
Chip Type
65510 Controller
256Kx16 DRAM
Total
Chips and Technologies, Inc. 2950 Zanker Road, San Jose, CA 95134 Telephone (408) 434-0600
Publication No.: PO20.1
Stock No: 067020-001
Revision: 1.1
Date: 7/31/95
65510
Flat Panel VGA Controller
Data Sheet
December 1992
P
R
E
L
I
M
I
N
A
R
Y
®
Copyright Notice
Copyright © 1992 Chips and Technologies, Inc. ALL RIGHTS RESERVED.
This manual is copyrighted by Chips and Technologies, Inc. You may not reproduce,
transmit, transcribe, store in a retrieval system, or translate into any language or
computer language, in any form or by any means, electronic, mechanical, magnetic,
optical, chemical, manual, or otherwise, any part of this publication without the
express written permission of Chips and Technologies, Inc.
Restricted Rights Legend
Use, duplication, or disclosure by the Government is subject to restrictions set forth
in subparagraph (c)(1)(ii) of the Rights in Technical Data and Computer Software
clause at 252.277-7013.
Trademark
Acknowledgement
CHIPS and NEAT are registered trademarks of Chips and Technologies, Inc.
CHIPS, CHIPSet, MICROCHIPS, SCAT, NEATsx, LeAPSet, LeAPSetsx, PEAK,
CHIPS/230, CHIPS/250, CHIPS/280, CHIPS/450, CHIPSPak, CHIPSPort,
CHIPSlink, SMARTMAP, and Wingine are trademarks of Chips and Technologies,
Incorporated.
IBM AT, XT, PS/2, Micro Channel, Personal System/2, Enhanced Graphics Adapter,
Color Graphics Adapter, Video Graphics Adapter, IBM Color Display, and IBM
Monochrome Display are trademarks of International Business Machines.
Hercules is a trademark of Hercules Computer Technology.
MS-DOS and Windows are trademarks of Microsoft, Incorporated.
MultiSync is a trademark of Nippon Electric Company (NEC).
Brooktree and RAMDAC are trademarks of Brooktree Corporation.
Inmos is a trademark of Inmos Corporation.
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
Disclaimer
This document is provided for the general information of the customer. Chips and
Technologies, Inc., reserves the right to modify the information contained herein as
necessary and the customer should ensure that it has the most recent revision of the
data sheet. CHIPS makes no warranty for the use of its products and bears no respon-
sibility for any errors which may appear in this document. The customer should be
on notice that the field of personal computers is the subject of many patents held by
different parties. Customers should ensure that they take appropriate action so that
their use of the products does not infringe upon any patents. It is the policy of Chips
and Technologies, Inc. to respect the valid patent rights of third parties and not to
infringe upon or assist others to infringe upon such rights.
®
65510
Flat Panel VGA Controller
n
Highly integrated Flat Panel controller
• Separate Address and Data buses
• Direct support for Dual or Single Scan panels
• Single clock source
• 100-pin package
n
n
n
n
n
n
n
n
n
n
n
n
n
Single 256Kx16 DRAM provides two-chip VGA
subsystem
Innovative clock "doubling" functionality
Memory options are (1) 256Kx16 DRAM or (4)
256Kx4 DRAMs
3.3V/5V memory interface for low power normal
mode of operation
3.3V/5V panel and bus interfaces to support a
variety of panels and buses
Register-programmable 4mA or 8mA drive on
bus data lines D0-15 and panel interface signals
Advanced power management features minimize
power consumption during normal operation
Dedicated input pin supports minimum power
operation in Suspend and Resume modes (less
than 500µA)
n
n
n
n
n
n
n
n
n
Integrated Multiple Bus Interface
• High-speed x86 SL PI Bus
• EISA/ISA (PC/AT) Bus
• Micro Channel (MC) Bus
• High Speed 386 SX/DX Local Bus
High performance resulting from buffered writes
(Write Buffer) and fast screen updates (internal
asynchronous 16-level FIFO)
16-bit display memory operations
n
n
n
CPU activity indicated for orderly power down
procedure
Generates 64 gray levels on Monochrome Panels
Supports 640x480, x400, x200 Dual Panel/Dual
Drive (D/D) and Single Panel/Single Drive (S/S)
LCD, Plasma, and EL Panels
Single clock source with rate multiplier function to
generate a wide range of dot clock frequencies for
low power operation
Programmable polynomial based Frame Rate
Control gray scale algorithm supports fast response
"mouse quick" displays by reducing flicker without
increasing panel vertical refresh rate
Programmable vertical compensation techniques
maximize display area
Intelligent SMARTMAP™ color to gray scale
conversion
Text Enhancement feature improves contrast of
text on flat panel displays
Three software selectable RGB color to gray scale
reduction techniques
Linearly Addressable Video Memory enables
utilization of high performance 32-bit software
drivers
Fully Compatible with IBM™ VGA
Full backwards compatability with EGA, CGA,
MDA, and Hercules graphics standards
Small low-cost package: EIAJ-standard 100-pin
plastic flat pack available in thin 20 mil lead pitch
or standard 25 mil lead pitch packages
Chip pinouts optimized for PCB layout
BIOS
ROM
Address
Data
Clock
65510
Control
Panel Control
Panel Data
256Kx16
DRAM
To Flat
Panel
Display
ISA, MC, x86 SL PI or
386 SX/DX Local Bus
System Diagram
Revision 0.7
Preliminary 65510
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