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TS80C51RA2-MIBR

Description
8-BIT, 40 MHz, MICROCONTROLLER, PQCC44
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size320KB,74 Pages
ManufacturerAtmel (Microchip)
Download Datasheet Parametric View All

TS80C51RA2-MIBR Overview

8-BIT, 40 MHz, MICROCONTROLLER, PQCC44

TS80C51RA2-MIBR Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerAtmel (Microchip)
Parts packaging codeLCC
package instructionQCCJ, LDCC44,.7SQ
Contacts44
Reach Compliance Codecompli
ECCN code3A991.A.2
Has ADCNO
Address bus width16
bit size8
CPU series8051
maximum clock frequency40 MHz
DAC channelNO
DMA channelNO
External data bus width8
JESD-30 codeS-PQCC-J44
JESD-609 codee0
length16.5862 mm
Humidity sensitivity level2
Number of I/O lines32
Number of terminals44
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
PWM channelYES
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Encapsulate equivalent codeLDCC44,.7SQ
Package shapeSQUARE
Package formCHIP CARRIER
Peak Reflow Temperature (Celsius)225
power supply5 V
Certification statusNot Qualified
RAM (bytes)512
rom(word)0
Maximum seat height4.57 mm
speed40 MHz
Maximum slew rate27 mA
Maximum supply voltage5.5 V
Minimum supply voltage4.5 V
Nominal supply voltage5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
width16.5862 mm
uPs/uCs/peripheral integrated circuit typeMICROCONTROLLER
TS80C51RA2/RD2
TS83C51RB2/RC2/RD2
TS87C51RB2/RC2/RD2
High Performance 8-bit Microcontrollers
1. Description
Atmel Wireless & Microcontrollers TS80C51Rx2 is high
performance CMOS ROM, OTP, EPROM and ROMless
versions of the 80C51 CMOS single chip 8-bit
microcontroller.
The TS80C51Rx2 retains all features of the 80C51 with
extended ROM/EPROM capacity (16/32/64 Kbytes), 256
bytes of internal RAM, a 7-source , 4-level interrupt
system, an on-chip oscilator and three timer/counters.
In addition, the TS80C51Rx2 has a Programmable
Counter Array, an XRAM of 256 or 768 bytes, a
Hardware Watchdog Timer, a more versatile serial
channel that facilitates multiprocessor communication
(EUART) and a X2 speed improvement mechanism.
The fully static design of the TS80C51Rx2 allows to
reduce system power consumption by bringing the clock
frequency down to any value, even DC, without loss of
data.
The TS80C51Rx2 has 2 software-selectable modes of
reduced activity for further reduction in power
consumption. In the idle mode the CPU is frozen while
the timers, the serial port and the interrupt system are still
operating. In the power-down mode the RAM is saved
and all other functions are inoperative.
2. Features
80C52 Compatible
8051 pin and instruction compatible
Four 8-bit I/O ports
Three 16-bit timer/counters
256 bytes scratchpad RAM
High-Speed Architecture
40 MHz @ 5V, 30MHz @ 3V
X2 Speed Improvement capability (6 clocks/
machine cycle)
30 MHz @ 5V, 20 MHz @ 3V (Equivalent to
60 MHz @ 5V, 40 MHz @ 3V)
Dual Data Pointer
Hardware Watchdog Timer (One-time enabled with
Reset-Out)
2 extra 8-bit I/O ports available on RD2 with high
pin count packages
Asynchronous port reset
Interrupt Structure with
7 Interrupt sources,
4 level priority interrupt system
Full duplex Enhanced UART
Framing error detection
Automatic address recognition
Low EMI (inhibit ALE)
On-chip ROM/EPROM (16K-bytes, 32K-bytes, 64K-
bytes)
Power Control modes
Idle mode
Power-down mode
Power-off Flag
Once mode (On-chip Emulation)
On-chip eXpanded RAM (XRAM) (256 or 768 bytes)
Programmable Clock Out and Up/Down Timer/
Counter 2
Programmable Counter Array with
High Speed Output,
Compare / Capture,
Pulse Width Modulator,
Watchdog Timer Capabilities
Power supply: 4.5-5V, 2.7-5.5V
Temperature ranges: Commercial (0 to 70
o
C) and
Industrial (-40 to 85
o
C)
Packages: PDIL40, PLCC44, VQFP44 1.4, CQPJ44
(window), CDIL40 (window), PLCC68, VQFP64
1.4, JLCC68 (window)
Rev. C - 06 March, 2001
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