SY58605U
3.2Gbps Precision, LVDS Buffer with
Internal Termination and Fail Safe Input
General Description
The SY58605U is a 2.5V, high-speed, fully differential
LVDS buffer optimized to provide less than 10ps
pp
total
jitter. The SY58605U can process clock signals as fast
as 2GHz or data patterns up to 3.2Gbps.
The differential input includes Micrel’s unique, 3-pin
input termination architecture that interfaces to LVPECL,
LVDS or CML differential signals, (AC- or DC-coupled)
as small as 100mV (200mV
pp
) without any level-shifting
or termination resistor networks in the signal path. For
AC-coupled input interface applications, an integrated
voltage reference (V
REF-AC
) is provided to bias the V
T
pin.
The output is 325mV LVDS, with rise/fall times
guaranteed to be less than 100ps.
The SY58605U operates from a 2.5V ±5% supply and is
guaranteed over the full industrial temperature range
(–40°C to +85°C). For applications that require CML or
LVPECL outputs, consider Micrel’s SY58603U and
SY58604U, buffers with 400mV and 800mV output
swings respectively. The SY58605U is part of Micrel’s
®
high-speed, Precision Edge product line.
Datasheets and support documentation can be found on
Micrel’s web site at:
www.micrel.com.
Precision Edge
®
Features
•
Precision 325mV LVDS buffer
•
Guaranteed AC performance over temperature and
voltage:
– DC-to > 3.2Gbps throughput
– <300ps typical propagation delay (IN-to-Q)
– <100ps rise/fall times
•
Fail Safe Input
– Prevents output from oscillating when input is
invalid
•
Ultra-low jitter design
– <1ps
RMS
cycle-to-cycle jitter
– <10ps
PP
total jitter
– <1ps
RMS
random jitter
– <10ps
PP
deterministic jitter
•
High-speed LVDS output
•
2.5V ±5% power supply operation
•
Industrial temperature range: –40°C to +85°C
•
Available in 8-pin (2mm x 2mm) DFN package
Functional Block Diagram
Applications
•
•
•
•
All SONET clock and data distribution
Fibre Channel clock and data distribution
Gigabit Ethernet clock and data distribution
Backplane distribution
Markets
•
•
•
•
•
•
•
Storage
ATE
Test and measurement
Enterprise networking equipment
High-end servers
Access
Metro area network equipment
Precision Edge is a registered trademark of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
August 2007
M9999-082907-B
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY58605U
Ordering Information
(1)
Part Number
SY58605UMG
SY58605UMGTR
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
A
= 25°C, DC Electricals only.
2. Tape and Reel.
(2)
Package
Type
DFN-8
DFN-8
Operating
Range
Industrial
Industrial
Package Marking
605 with Pb-Free
bar-line indicator
605 with Pb-Free
bar-line indicator
Lead
Finish
NiPdAu
Pb-Free
NiPdAu
Pb-Free
Pin Configuration
8-Pin DFN
Pin Description
Pin Number
1, 4
Pin Name
IN, /IN
Pin Function
Differential Input: This input pair is the differential signal input to the device. Input
accepts DC-coupled differential signals as small as 100mV (200mV
PP
). Each pin of
this pair internally terminates with 50Ω to the VT pin. If the input swing falls
below a
certain threshold (typically 30mV), them the Fail Safe Input (FSI) feature will
guarantee a stable output by latching the output to its last valid state. See “Input
Interface Applications” subsection for more details.
Input Termination Center-Tap: Each input terminates to this pin. The V
T
pin provides
a center-tap for each input (IN, /IN) to a termination network for maximum interface
flexibility. See “Input Interface Applications” subsection for more details.
Reference Voltage: This output biases to V
CC
–1.2V. It is used for AC-coupling input
IN and /IN. Connect VREF-AC directly to the VT pin. Bypass with 0.01µF low ESR
capacitor to VCC. Maximum sink/source current is ±1.5mA. See “Input Interface
Applications” subsection for more details.
Ground: Exposed pad must be connected to a ground plane that is the same
potential as the ground pin.
LVDS Differential Output Pair: The output swing is typically 325mV. Normally
terminated with 100Ω
across the pair (Q, /Q). See “LVDS Output Termination”
subsection for more details.
Positive Power Supply: Bypass with 0.1µF//0.01µF low ESR capacitors as close to
the V
CC
pin as possible.
2
VT
3
VREF-AC
5
6, 7
GND,
Exposed pad
/Q, Q
8
VCC
August 2007
2
M9999-082907-B
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY58605U
Absolute Maximum Ratings
(1)
Supply Voltage (V
CC
) ............................... –0.5V to +4.0V
Input Voltage (V
IN
) ............................ –0.5V to V
CC
+0.3V
LVDS Output Current (I
OUT
) .................................. ±10mA
Input Current
Source or Sink Current on (IN, /IN) ............... ±50mA
Current (V
REF
)
(4)
Source or sink current on V
REF-AC
.............. ±1.5mA
Maximum operating Junction Temperature .......... 125°C
Lead Temperature (soldering, 20sec.) .................. 260°C
Storage Temperature (T
s
) .................... –65°C to +150°C
Operating Ratings
(2)
Supply Voltage (V
IN
) ...................... +2.375V to +2.625V
Ambient Temperature (T
A
) ................... –40°C to +85°C
(3)
Package Thermal Resistance
DFN
Still-air (θ
JA
) ............................................ 93°C/W
Junction-to-board (ψ
JB
) .......................... 56°C/W
DC Electrical Characteristics
(5)
T
A
= –40°C to +85°C, unless otherwise stated.
Symbol
V
CC
I
CC
R
DIFF_IN
V
IH
V
IL
V
IN
V
DIFF_IN
V
IN_FSI
V
REF-AC
V
T_IN
Notes:
1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not
implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for
extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB.
ψ
JB
and
θ
JA
values are determined for a 4-layer board in still-air number, unless otherwise stated.
4. Due to the limited drive capability, use for input of the same package only.
5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
6. V
IN
(max) is specified when V
T
is floating.
Parameter
Power Supply Voltage Range
Power Supply Current
Differential Input Resistance
(IN-to-/IN)
Input HIGH Voltage
(IN, /IN)
Input LOW Voltage
(IN, /IN)
Input Voltage Swing
(IN, /IN)
Differential Input Voltage Swing
(|IN - /IN|)
Input Voltage Threshold that
Triggers FSI
Output Reference Voltage
Voltage from Input to V
T
Condition
No load, max. V
CC
Min
2.375
Typ
2.5
35
Max
2.625
50
110
V
CC
V
IH
–0.1
1.7
Units
V
mA
Ω
V
V
V
V
90
IN, /IN
IN, /IN
see Figure 3a, Note 6
see Figure 3b
1.2
0
0.1
0.2
100
30
V
CC
–1.3
V
CC
–1.2
100
V
CC
–1.1
1.28
mV
V
V
August 2007
3
M9999-082907-B
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY58605U
LVDS Output DC Electrical Characteristics
(7)
V
CC
= +2.5V ±5%, R
L
= 100Ω
across the outputs; T
A
= –40°C to +85°C, unless otherwise stated.
Symbol
V
OUT
V
DIFF_OUT
V
OCM
Δ
VOCM
Note:
7. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Parameter
Output Voltage Swing
Differential Output Voltage Swing
Output Common Mode Voltage
Change in Common Mode
Voltage
Condition
See Figure 3a
See Figure 3b
Min
250
500
1.125
-50
Typ
325
650
1.20
Max
Units
mV
mV
1.275
50
V
mV
August 2007
4
M9999-082907-B
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY58605U
AC Electrical Characteristics
V
CC
= +2.5V ±5%, R
L
= 100Ω
across the outputs, Input t
r
/t
f
: <300ps; T
A
= –40°C to +85°C, unless otherwise stated.
Symbol
f
MAX
t
PD
t
Skew
t
Jitter
Parameter
Maximum Frequency
Propagation Delay
Part-to-Part Skew
Data
Clock
t
r,
t
f
Random Jitter
Deterministic Jitter
Cycle-to-Cycle Jitter
Total Jitter
Output Rise/Fall Times
(20% to 80%)
Duty Cycle
Notes:
8.
9.
Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges at the
respective inputs.
Random jitter is measured with a K28.7 pattern, measured at
≤ f
MAX
.
Condition
NRZ Data
V
OUT
> 200mV
IN-to-Q
V
IN
: 100mV-200mV
200mV-800mV
Note 8
Note 9
Note 10
Note 11
Note 12
At full output swing.
Differential I/O
Clock
Min
3.2
2.0
170
130
Typ
3
280
200
Max
Units
Gbps
GHz
420
300
135
1
10
1
10
ps
ps
ps
ps
RMS
ps
PP
ps
RMS
ps
PP
ps
%
35
47
60
100
53
10. Deterministic jitter is measured at 2.5Gbps with both K28.5 and 2
23
–1 PRBS pattern.
11. Cycle-to-cycle jitter definition: the variation period between adjacent cycles over a random sample of adjacent cycle pairs. t
JITTER
_
CC
= T
n
–T
n+1
,
where T is the time between rising edges of the output signal.
12. Total jitter definition: with an ideal clock input frequency of
≤ f
MAX
(device), no more than one output edge in 10
12
output edges will deviate by
more than the specified peak-to-peak jitter value.
August 2007
5
M9999-082907-B
hbwhelp@micrel.com
or (408) 955-1690
京公网安备 11010802033920号
EEWORLD
