Preliminary
Datasheet
Specifications in this document are tentative and subject to change.
RL78/G1A
RENESAS MCU
R01DS0151EJ0001
Rev.0.01
2011.12.26
Combines Multi-channel 12-Bit A/D Converter, True Low Power Platform (as low as 66
µA/MHz,
and
0.57
µA
for RTC + LVD), 1.6 V to 3.6 V operation, 16 to 64 Kbyte Flash, 41 DMIPS at 32 MHz
1.
1.1
OUTLINE
Features
Data Memory Access (DMA) Controller
•
Up to 2 fully programmable channels
•
Transfer unit: 8- or 16-bit
Multiple Communication Interfaces
•
Up to 6 x I
2
C master
2
•
Up to 1 x I C multi-master
•
Up to 6 x CSI/SPI (7-, 8-bit)
•
Up to 3 x UART (7-, 8-, 9-bit)
•
Up to 1 x LIN
Extended-Function Timers
•
Multi-function 16-bit timers: Up to 8 channels
•
Real-time clock (RTC): 1 channel (full calendar and
alarm function with watch correction function)
•
Interval Timer: 12-bit, 1 channel
•
15 kHz watchdog timer: 1 channel (window function)
Rich Analog
•
ADC: Up to 28 channels, 12-bit resolution, 3.375
µs
conversion time
•
Supports 1.6 V
•
Internal voltage reference (1.45 V)
•
On-chip temperature sensor
Safety Features (IEC or UL 60730 compliance)
•
Flash memory CRC calculation
•
RAM parity error check
•
RAM write protection
•
SFR write protection
•
Illegal memory access detection
•
Clock stop/ frequency detection
•
ADC self-test
General Purpose I/O
•
3.6 V tolerant, high-current (up to 20 mA per pin)
•
Open-Drain, Internal Pull-up support
Operating Ambient Temperature
•
Standard:
−40
°C to +85 °C
Package Type and Pin Count
From 3 mm x 3 mm to 10 mm x 10 mm
QFP: 48, 64
QFN: 32, 48
LGA: 25
BGA: 64
Ultra-Low Power Technology
•
1.6 V to 3.6 V operation from a single supply
•
Stop (RAM retained): 0.23
µA,
(LVD enabled): 0.31
µA
•
Halt (RTC + LVD): 0.57
µA
•
Snooze: T.B.D.
•
Operating: 66
µA/MHz
16-bit RL78 CPU Core
•
Delivers 41 DMIPS at maximum operating frequency
of 32 MHz
•
Instruction Execution: 86% of instructions can be
executed in 1 to 2 clock cycles
•
CISC Architecture (Harvard) with 3-stage pipeline
•
Multiply Signed & Unsigned: 16 x 16 to 32-bit result in
1 clock cycle
•
MAC: 16 x 16 to 32-bit result in 2 clock cycles
•
16-bit barrel shifter for shift & rotate in 1 clock cycle
•
1-wire on-chip debug function
Code Flash Memory
•
Density: 16 KB to 64 KB
•
Block size: 1 KB
•
On-chip single voltage flash memory with protection
from block erase/writing
•
Self-programming with secure boot swap function
and flash shield window function
Data Flash Memory
•
Data Flash with background operation
•
Data flash size: 4 KB
•
Erase Cycles: 1 Million (typ.)
•
Erase/programming voltage: 1.8 V to 3.6 V
RAM
•
2 KB to 4 KB size options
•
Supports operands or instructions
•
Back-up retention in all modes
High-speed On-chip Oscillator
•
32 MHz with +/− 1% accuracy over voltage (1.8 V to
3.6 V) and temperature (−20 °C to +85 °C)
•
Pre-configured settings: 32 MHz, 24 MHz, 16 MHz,
12 MHz, 8 MHz, 4 MHz & 1 MHz
Reset and Supply Management
•
Power-on reset (POR) monitor/generator
•
Low voltage detection (LVD) with 12 setting options
(Interrupt and/or reset function)
R01DS0151EJ0001 Rev.0.01
2011.12.26
Page 1 of 76
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/G1A
1. OUTLINE
1.2
Ordering Information
•
Flash memory version (lead-free product)
Pin count
25 pins
Package
25-pin plastic FLGA (3
×
3)
Data flash
Mounted
Part Number
R5F10E8AALA, R5F10E8CALA, R5F10E8DALA,
R5F10E8EALA
32 pins
32-pin plastic WQFN (fine pitch)
(5
×
5)
Mounted
R5F10EBAANA, R5F10EBCANA, R5F10EBDANA,
R5F10EBEANA
48 pins
48-pin plastic LQFP (fine pitch)
(7
×
7)
48-pin plastic WQFN (7
×
7)
Mounted
R5F10EGAAFB, R5F10EGCAFB, R5F10EGDAFB,
R5F10EGEAFB
Mounted
R5F10EGAANA, R5F10EGCANA, R5F10EGDANA,
R5F10EGEANA
64 pins
64-pin plastic LQFP (fine pitch)
(10
×
10)
64-pin plastic FBGA (4
×
4)
Mounted
R5F10ELCAFB, R5F10ELDAFB, R5F10ELEAFB
Mounted
R5F10ELCABG, R5F10ELDABG, R5F10ELEABG
R01DS0151EJ0001 Rev.0.01
2011.12.26
Page 3 of 76
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/G1A
1. OUTLINE
1.3.2
32-pin products
•
32-pin plastic WQFN (fine pitch) (5
×
5)
AV
SS
AV
DD
P10/ANI18/SCK00/SCL00/(KR0)
P11/ANI20/SI00/SDA00/RxD0/TOOLRxD/(KR1)
P12/ANI21/SO00/TxD0/TOOLTxD/(KR2)
P13/ANI22/SO20/TxD2/(KR3)
P14/ANI23/SI20/SDA20/RxD2/(KR4)
P15/ANI24/SCK20/SCL20/PCLBUZ1/(KR5)
exposed die pad
P24/ANI4/(KR5)
P23/ANI3/(KR4)
P22/ANI2/(KR3)
P21/ANI1/AV
REFM
P20/ANI0/AV
REFP
P03/ANI16/RxD1/TO00/(KR2)
P02/ANI17/TxD1/TI00/(KR1)
P120/ANI19/(KR0)
24 23 22 21 20 19 18 17
25
16
26
15
27
14
28
13
29
12
30
11
31
10
32
9
1 2 3 4 5 6 7 8
P51/SO11/INTP2
P50/ANI26/SI11/SDA11/INTP1
P30/ANI27/SCK11/SCL11/INTP3
P70/ANI28/KR0
P31/ANI29/TI03/TO03/PCLBUZ0/INTP4
P62
P61/SDAA0
P60/SCLA0
Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1
μ
F).
Remarks 1.
For pin identification, see
1.4
redirection register (PIOR).
Pin Identification.
2.
Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
P40/TOOL0
RESET
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
V
SS
V
DD
R01DS0151EJ0001 Rev.0.01
2011.12.26
Page 5 of 76
Analogue and Mixed Signal
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