R5F10ELCABG datasheet, PDF - EEWORLD Datasheet

R5F10ELCABG: DescriptionCombines Multi-channel 12-Bit A/D Converter, True Low Power Platform (as low as 66 Î¼A/MHz, and 0.57 Î¼A for RTC LVD), 1.6 V to 3.6 V operation, 16 to 64 Kbyte Flash, 41 DMIPS at 32 MHz; File Size940KB，79 Pages; ManufacturerRenesas Electronics Corporation; Websitehttps://www.renesas.com/

Download Datasheet View All

R5F10ELCABG Overview

Combines Multi-channel 12-Bit A/D Converter, True Low Power Platform (as low as 66 Î¼A/MHz, and 0.57 Î¼A for RTC LVD), 1.6 V to 3.6 V operation, 16 to 64 Kbyte Flash, 41 DMIPS at 32 MHz

Preview

Download Datasheet

View All

Preliminary

Datasheet

Specifications in this document are tentative and subject to change.

RL78/G1A

RENESAS MCU

R01DS0151EJ0001

Rev.0.01

2011.12.26

Combines Multi-channel 12-Bit A/D Converter, True Low Power Platform (as low as 66

µA/MHz,

and

0.57

µA

for RTC + LVD), 1.6 V to 3.6 V operation, 16 to 64 Kbyte Flash, 41 DMIPS at 32 MHz

1.1

OUTLINE

Features

Data Memory Access (DMA) Controller

•

Up to 2 fully programmable channels

•

Transfer unit: 8- or 16-bit

Multiple Communication Interfaces

•

Up to 6 x I

C master

•

Up to 1 x I C multi-master

•

Up to 6 x CSI/SPI (7-, 8-bit)

•

Up to 3 x UART (7-, 8-, 9-bit)

•

Up to 1 x LIN

Extended-Function Timers

•

Multi-function 16-bit timers: Up to 8 channels

•

Real-time clock (RTC): 1 channel (full calendar and

alarm function with watch correction function)

•

Interval Timer: 12-bit, 1 channel

•

15 kHz watchdog timer: 1 channel (window function)

Rich Analog

•

ADC: Up to 28 channels, 12-bit resolution, 3.375

µs

conversion time

•

Supports 1.6 V

•

Internal voltage reference (1.45 V)

•

On-chip temperature sensor

Safety Features (IEC or UL 60730 compliance)

•

Flash memory CRC calculation

•

RAM parity error check

•

RAM write protection

•

SFR write protection

•

Illegal memory access detection

•

Clock stop/ frequency detection

•

ADC self-test

General Purpose I/O

•

3.6 V tolerant, high-current (up to 20 mA per pin)

•

Open-Drain, Internal Pull-up support

Operating Ambient Temperature

•

Standard:

−40

°C to +85 °C

Package Type and Pin Count

From 3 mm x 3 mm to 10 mm x 10 mm

QFP: 48, 64

QFN: 32, 48

LGA: 25

BGA: 64

Ultra-Low Power Technology

•

1.6 V to 3.6 V operation from a single supply

•

Stop (RAM retained): 0.23

µA,

(LVD enabled): 0.31

µA

•

Halt (RTC + LVD): 0.57

µA

•

Snooze: T.B.D.

•

Operating: 66

µA/MHz

16-bit RL78 CPU Core

•

Delivers 41 DMIPS at maximum operating frequency

of 32 MHz

•

Instruction Execution: 86% of instructions can be

executed in 1 to 2 clock cycles

•

CISC Architecture (Harvard) with 3-stage pipeline

•

Multiply Signed & Unsigned: 16 x 16 to 32-bit result in

1 clock cycle

•

MAC: 16 x 16 to 32-bit result in 2 clock cycles

•

16-bit barrel shifter for shift & rotate in 1 clock cycle

•

1-wire on-chip debug function

Code Flash Memory

•

Density: 16 KB to 64 KB

•

Block size: 1 KB

•

On-chip single voltage flash memory with protection

from block erase/writing

•

Self-programming with secure boot swap function

and flash shield window function

Data Flash Memory

•

Data Flash with background operation

•

Data flash size: 4 KB

•

Erase Cycles: 1 Million (typ.)

•

Erase/programming voltage: 1.8 V to 3.6 V

RAM

•

2 KB to 4 KB size options

•

Supports operands or instructions

•

Back-up retention in all modes

High-speed On-chip Oscillator

•

32 MHz with +/− 1% accuracy over voltage (1.8 V to

3.6 V) and temperature (−20 °C to +85 °C)

•

Pre-configured settings: 32 MHz, 24 MHz, 16 MHz,

12 MHz, 8 MHz, 4 MHz & 1 MHz

Reset and Supply Management

•

Power-on reset (POR) monitor/generator

•

Low voltage detection (LVD) with 12 setting options

(Interrupt and/or reset function)

R01DS0151EJ0001 Rev.0.01

2011.12.26

Page 1 of 76

Recommended Resources

Pulse signal generating circuit b

PC communication interface circuit using RS-422A interface standard

Coin heads and tails indicator

Bass modulation amplifier circuit

Delay circuit using a field effect transistor

Non-polar electrolytic capacitor aging circuit

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components