Preliminary
Datasheet
Specifications in this document are tentative and subject to change.
R8C/56E Group, R8C/56F Group, R8C/56G Group, R8C/56H Group
RENESAS MCU
R01DS0042EJ0010
Rev.0.10
Mar 15, 2011
1.
1.1
Overview
Features
The R8C/56E Group, R8C/56F Group, R8C/56G Group, R8C/56H Group single-chip microcontrollers (MCUs)
incorporate the R8C CPU core, which provides sophisticated instructions for a high level of efficiency. With 1
Mbyte of address space, the CPU core is capable of executing instructions at high speed. In addition, it features a
multiplier for high-speed arithmetic processing.
Power consumption is low, and additional power control is possible by selecting the operating mode. The R8C/56E
Group, R8C/56F Group, R8C/56G Group, R8C/56H Group are also designed to maximize EMI/EMS performance.
Integration of many peripheral functions, including multifunction timer and serial interface on the same chip,
reduces the number of system components.
The R8C/56E Group and R8C/56F Group incorporate one channel of CAN module, ideal for the LAN systems of
automotive and factory automation applications.
The R8C/56G Group and R8C/56H Group do not incorporate the CAN module.
The R8C/56E Group and R8C/56G Group also have on-chip data flash (1 KB × 4 blocks) with background
operation (BGO) function.
1.1.1
Applications
Automotive, etc.
R01DS0042EJ0010 Rev.0.10
Mar 15, 2011
Page 1 of 58
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/56E Group, R8C/56F Group, R8C/56G Group, R8C/56H Group
1. Overview
1.1.2
Specifications
Tables 1.1 to 1.3 outline the R8C/56E Group Specifications. Tables 1.4 to 1.6 outline the R8C/56F Group
Specifications. Tables 1.7 to 1.9 outline the R8C/56G Group Specifications. Tables 1.10 to 1.12 outline the
R8C/56H Group Specifications.
Table 1.1
Item
CPU
R8C/56E Group Specifications (1)
Function
Central
processing unit
Description
R8C CPU core
• Number of fundamental instructions: 89
• Minimum instruction execution time:
31.25 ns (CPU clock = 32 MHz, VCC = 2.7 V to 5.5 V)
200 ns (CPU clock = 5 MHz, VCC = 1.8 V to 2.7 V)
• Multiplier: 16 bits × 16 bits
32 bits
• Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits
32 bits
• Operating mode: Single-chip mode (address space: 1 Mbyte)
See
Table 1.13 R8C/56E Group Product List.
ROM, RAM,
data flash
Voltage
Voltage detection • Power-on reset
detection
circuit
• Voltage detection with three check points (the detection levels for voltage
detection 0 and voltage detection 1 can be selected.)
I/O ports
Programmable
• Input only: 1
I/O ports
• CMOS I/O: 59, selectable pull-up resistor
• Simplified peripheral mapping controller (PMC) allows either timer priority or
communication function priority pin assignment selection.
Clock
Clock generation • 4 circuits: XIN clock oscillation circuit,
circuits
high-speed on-chip oscillator (with frequency adjustment function),
low-speed on-chip oscillator,
PLL frequency synthesizer (up to 32 MHz), multiplied by 2, 4, 6, or 8
• Oscillation stop detection: XIN clock oscillation stop detection function
• Frequency divider circuit: Divided by 1, 2, 4, 8, or 16 can be selected
• Low-power mode: Standard operating mode (high-speed clock, high-speed
on-chip oscillator, low-speed on-chip oscillator), wait mode,
stop mode
Interrupts
• Number of interrupt vectors: 69
• External interrupt inputs: 9 (INT × 5, key input × 4)
• Priority levels: 7
Event link controller (ELC)
• Events output from peripheral functions can be linked to events input to
different peripheral functions.
(30 sources × 10 types of event link operations)
• Events can be handled independently from interrupt requests.
Watchdog timer
• 14 bits × 1
• Selectable reset start function
• Selectable low-speed on-chip oscillator for the watchdog timer
DTC (data transfer controller)
• 1 channel
• Activation sources: 42
• Transfer modes: 2 (normal mode, repeat mode)
Memory
R01DS0042EJ0010 Rev.0.10
Mar 15, 2011
Page 2 of 58
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/56E Group, R8C/56F Group, R8C/56G Group, R8C/56H Group
1. Overview
Table 1.2
Item
Timer
R8C/56E Group Specifications (2)
Function
Description
Timers RJ_0 and 16 bits × 1: 2 circuits integrated on-chip
RJ_1
Timer mode (periodic timer), pulse output mode (output level inverted every
period), event counter mode, pulse width measurement mode, pulse period
measurement mode
Timer RB2_0
16 bits × 1: 1 circuits integrated on-chip
Timer mode (periodic timer), programmable waveform generation mode
(PWM output), programmable one-shot generation mode, programmable wait
one-shot generation mode
Timers RC_0 and 16 bits (with 4 capture/compare registers) × 1: 2 circuits integrated on-chip
RC_1
Timer mode (input capture function, output compare function), PWM mode
(output: 3 pins), PWM2 mode (PWM output: 1 pin)
(2 channels can be used only when 64 pins and timer function priority pin
assignment are selected (only 1 channel for others))
Timer RD_0
16 bits (with 4 capture/compare registers) × 2: 1 circuit integrated on-chip
Timer mode (input capture function, output compare function), PWM mode
(output: 6 pins), reset synchronous PWM mode (three-phase waveform output
(6 pins), sawtooth wave modulation), complementary PWM mode (three-
phase waveform output (6 pins), triangular wave modulation), PWM3 mode
(PWM output with fixed period: 2 pins)
Timer RE2
8 bits × 1
Compare match timer mode
Timer RF
16 bits × 1
Input capture function mode (input capture function), output compare mode
(output compare function)
Timer RG
16 bits × 1
Timer mode (input capture function, output compare function),
PWM mode (output: 1 pin), phase counting mode (the counts of the 2-phase
encoder can be automatically counted.)
Serial interface UART0_0 and
2 channels
UART0_1
Clock synchronous serial I/O mode, clock asynchronous serial I/O mode
1 channel
UART2
Clock synchronous serial I/O mode, clock asynchronous serial I/O mode,
special mode 3 (IE mode), multiprocessor communication mode
Clock
(SSU)
2 channels (also used for the I
2
C bus)
Synchronous
SSU_0 and
(2 channels can be used only for communication function priority pin assignment
SSU_1
serial
(only 1 channel for others))
interface
2 channels (also used for the SSU)
(I
2
C bus)
I
2
C_0 and I
2
C_1 (2 channels can be used only for communication function priority pin assignment
(only 1 channel for others))
LIN
HW-LIN_0 and
Hardware LIN
module
HW-LIN_1
2 channels (Timers RJ_0 and RJ_1, UART0_0 and UART0_1 are used)
CAN module
CAN_0
1 channel: 16 mailboxes (ISO11898-1 standard compliant)
A/D converter
Resolution: 10 bits × 16 channels, sample and hold function, sweep mode
Comparator B
2 circuits
CRC calculator
CRC-CCITT (X
16
+ X
12
+ X
5
+ 1), CRC-16 (X
16
+ X
15
+ X
2
+ 1) compliant
Flash memory
• Program/erase voltage: VCC = 2.7 V to 5.5 V
• Read voltage: VCC = 1.8 V to 5.5 V
• Program/erase endurance:10,000 times (data flash)
1,000 times (program ROM)
• Program security: ROM code protect, ID code check
• Debug functions: On-chip debug, on-board flash rewrite function
• BGO (background operation) function (data flash)
R01DS0042EJ0010 Rev.0.10
Mar 15, 2011
Page 3 of 58
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/56E Group, R8C/56F Group, R8C/56G Group, R8C/56H Group
1. Overview
Table 1.3
R8C/56E Group Specifications (3)
Function
Description
• 1-wire debug interface provided (dedicated hardware provided)
• Hot plug connection is supported, allowing the debugger interface to be
connected during user mode operation.
CPU clock = 32 MHz (VCC = 2.7 V to 5.5 V)
CPU clock = 5 MHz (VCC = 1.8 V to 2.7 V)
T.B.D.
-40
C
to 85
C
(J version)
-40
C
to 125
C
(K version)
(1)
64-pin LQFP
Package code: PLQP0064KB-A (previous code: 64P6Q-A)
Item
Debug functions
Operating frequency/
Power supply voltage
Current consumption
Operating ambient temperature
Package
Note:
1. Specify the K version if it is to be used.
R01DS0042EJ0010 Rev.0.10
Mar 15, 2011
Page 4 of 58
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/56E Group, R8C/56F Group, R8C/56G Group, R8C/56H Group
1. Overview
Table 1.4
Item
CPU
R8C/56F Group Specifications (1)
Function
Central
processing unit
Description
R8C CPU core
• Number of fundamental instructions: 89
• Minimum instruction execution time:
31.25 ns (CPU clock = 32 MHz, VCC = 2.7 V to 5.5 V)
200 ns (CPU clock = 5 MHz, VCC = 1.8 V to 2.7 V)
• Multiplier: 16 bits × 16 bits
32 bits
• Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits
32 bits
• Operating mode: Single-chip mode (address space: 1 Mbyte)
Memory
ROM, RAM
See
Table 1.14 R8C/56F Group Product List.
Voltage
Voltage detection • Power-on reset
detection
circuit
• Voltage detection with three check points (the detection levels for voltage
detection 0 and voltage detection 1 can be selected.)
I/O ports
Programmable
• Input only: 1
I/O ports
• CMOS I/O: 59, selectable pull-up resistor
• Simplified peripheral mapping controller (PMC) allows either timer priority or
communication function priority pin assignment selection.
Clock
Clock generation • 4 circuits: XIN clock oscillation circuit,
circuits
high-speed on-chip oscillator (with frequency adjustment function),
low-speed on-chip oscillator,
PLL frequency synthesizer (up to 32 MHz), multiplied by 2, 4, 6, or 8
• Oscillation stop detection: XIN clock oscillation stop detection function
• Frequency divider circuit: Divided by 1, 2, 4, 8, or 16 can be selected
• Low-power mode: Standard operating mode (high-speed clock, high-speed
on-chip oscillator, low-speed on-chip oscillator), wait mode,
stop mode
Interrupts
• Number of interrupt vectors: 69
• External interrupt inputs: 9 (INT × 5, key input × 4)
• Priority levels: 7
Event link controller (ELC)
• Events output from peripheral functions can be linked to events input to
different peripheral functions.
(30 sources × 10 types of event link operations)
• Events can be handled independently from interrupt requests.
Watchdog timer
• 14 bits × 1
• Selectable reset start function
• Selectable low-speed on-chip oscillator for the watchdog timer
DTC (data transfer controller)
• 1 channel
• Activation sources: 42
• Transfer modes: 2 (normal mode, repeat mode)
R01DS0042EJ0010 Rev.0.10
Mar 15, 2011
Page 5 of 58
Embedded System
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