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TS80C32X2-LIBR

Description
Connector
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size253KB,54 Pages
ManufacturerTEMIC
Websitehttp://www.temic.de/
Download Datasheet Parametric View All

TS80C32X2-LIBR Overview

Connector

TS80C32X2-LIBR Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerTEMIC
package instructionPLASTIC, LCC-44
Reach Compliance Codeunknow
Has ADCNO
Address bus width16
bit size8
CPU series8051
maximum clock frequency30 MHz
DAC channelNO
DMA channelNO
External data bus width8
JESD-30 codeR-PDIP-T40
JESD-609 codee0
Number of I/O lines32
Number of terminals40
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
PWM channelNO
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Encapsulate equivalent codeLDCC44,.7SQ
Package shapeRECTANGULAR
Package formIN-LINE
power supply3/5 V
Certification statusNot Qualified
RAM (bytes)256
rom(word)0
speed30 MHz
Maximum slew rate13 mA
Maximum supply voltage5.5 V
Minimum supply voltage2.7 V
surface mountNO
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formTHROUGH-HOLE
Terminal pitch1.27 mm
Terminal locationDUAL
uPs/uCs/peripheral integrated circuit typeMICROCONTROLLER
TS80C52X2
8-bit CMOS Microcontroller 0-60 MHz
1. Description
TEMIC TS80C52X2 is high performance CMOS ROM,
OTP, EPROM and ROMless versions of the 80C51
CMOS single chip 8-bit microcontroller.
The TS80C52X2 retains all features of the TEMIC
80C51 with extended ROM/EPROM capacity (8
Kbytes), 256 bytes of internal RAM, a 6-source , 4-level
interrupt system, an on-chip oscilator and three timer/
counters.
In addition, the TS80C52X2 has a dual data pointer, a
more versatile serial channel that facilitates
multiprocessor communication (EUART) and a X2 speed
improvement mechanism.
The fully static design of the TS80C52X2 allows to
reduce system power consumption by bringing the clock
frequency down to any value, even DC, without loss of
data.
The TS80C52X2 has 2 software-selectable modes of
reduced activity for further reduction in power
consumption. In the idle mode the CPU is frozen while
the timers, the serial port and the interrupt system are still
operating. In the power-down mode the RAM is saved
and all other functions are inoperative.
2. Features
q
80C52 Compatible
8051 pin and instruction compatible
Four 8-bit I/O ports
Three 16-bit timer/counters
256 bytes scratchpad RAM
q
Interrupt Structure with
6 Interrupt sources,
4 level priority interrupt system
q
Full duplex Enhanced UART
Framing error detection
Automatic address recognition
q
High-Speed Architecture
40 MHz @ 5V, 30MHz @ 3V
X2 Speed Improvement capability (6 clocks/
machine cycle)
30 MHz @ 5V, 20 MHz @ 3V (Equivalent to
60 MHz @ 5V, 40 MHz @ 3V)
q
q
Low EMI (inhibit ALE)
Power Control modes
Idle mode
Power-down mode
Power-off Flag
q
q
q
Dual Data Pointer
On-chip ROM/EPROM (8K-bytes)
Programmable Clock Out and Up/Down Timer/
Counter 2
Asynchronous port reset
q
q
q
q
Once mode (On-chip Emulation)
Power supply: 4.5-5V, 2.7-5.5V
Temperature ranges: Commercial (0 to 70
o
C) and
Industrial (-40 to 85
o
C)
Packages: PDIL40, PLCC44, VQFP44 1.4, PQFP F1
(13.9 footprint), CQPJ44 (window), CDIL40
(window)
q
Rev. B - Jan. 25, 1999
1
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