TS80C31X2-MCER datasheet, PDF - EEWORLD Datasheet

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TS80C31X2-MCER: Description8-bit CMOS Microcontroller 0-60 MHz; CategoryThe embedded processor and controller Microcontrollers and processors; File Size189KB，40 Pages; ManufacturerTEMIC; Websitehttp://www.temic.de/

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TS80C31X2-MCER Overview

8-bit CMOS Microcontroller 0-60 MHz

TS80C31X2-MCER Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	TEMIC
package instruction	VQFP-44
Reach Compliance Code	unknow
Has ADC	NO
Address bus width	16
bit size	8
CPU series	8051
maximum clock frequency	40 MHz
DAC channel	NO
DMA channel	NO
External data bus width	8
JESD-30 code	S-PQFP-G44
JESD-609 code	e0
Number of I/O lines	32
Number of terminals	44
Maximum operating temperature	70 °C
Minimum operating temperature
PWM channel	NO
Package body material	PLASTIC/EPOXY
encapsulated code	QFP
Encapsulate equivalent code	QFP44,.47SQ,32
Package shape	SQUARE
Package form	FLATPACK
power supply	5 V
Certification status	Not Qualified
RAM (bytes)	128
rom(word)	0
speed	40 MHz
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	QUAD
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER

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TS80C31X2

8-bit CMOS Microcontroller 0-60 MHz

1. Description

TEMIC TS80C31X2 is high performance CMOS and

ROMless versions of the 80C51 CMOS single chip 8-

bit microcontroller.

The TS80C31X2 retains all features of the TEMIC

TSC80C31 with 128 bytes of internal RAM, a 5-source,

4 priority level interrupt system, an on-chip oscilator

and two timer/counters.

In addition, the TS80C31X2 has a dual data pointer, a

more versatile serial channel that facilitates

multiprocessor communication (EUART) and a X2 speed

improvement mechanism.

The fully static design of the TS80C31X2 allows to

reduce system power consumption by bringing the clock

frequency down to any value, even DC, without loss of

data.

The TS80C31X2 has 2 software-selectable modes of

reduced activity for further reduction in power

consumption. In the idle mode the CPU is frozen while

the timers, the serial port and the interrupt system are still

operating. In the power-down mode the RAM is saved

and all other functions are inoperative.

2. Features

80C31 Compatible

•

8031 pin and instruction compatible

•

Four 8-bit I/O ports

•

Two 16-bit timer/counters

•

128 bytes scratchpad RAM

Interrupt Structure with

•

5 Interrupt sources,

•

4 priority level interrupt system

Full duplex Enhanced UART

•

Framing error detection

•

Automatic address recognition

High-Speed Architecture

•

40 MHz @ 5V, 30MHz @ 3V

•

X2 Speed Improvement capability (6 clocks/

machine cycle)

30 MHz @ 5V, 20 MHz @ 3V (Equivalent to

60 MHz @ 5V, 40 MHz @ 3V)

Power Control modes

•

Idle mode

•

Power-down mode

•

Power-off Flag

Dual Data Pointer

Asynchronous port reset

Once mode (On-chip Emulation)

Power supply: 4.5-5.5V, 2.7-5.5V

Temperature ranges: Commercial (0 to 70

C) and

Industrial (-40 to 85

Packages: PDIL40, PLCC44, VQFP44 1.4, PQFP F1

(13.9 footprint)

Rev. A - Mar. 19, 1999

Preliminary

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