HT83XXX
Q-Voice
TM
Technical Document
·
Tools Information
·
FAQs
·
Application Note
Features
·
Operating voltage: 2.4V~5.2V
·
Up to 1ms (0.5ms) instruction cycle with 4MHz (8MHz)
·
Watchdog Timer
·
4-level subroutine nesting
·
HALT function and wake-up feature reduce power
system clock
·
System clock: 4MHz~8MHz (2.4V)
·
Crystal or RC oscillator for system clock
·
12 I/O pins
·
2K´15 program ROM
·
80´8 RAM
·
Two 8-bit programmable timer counter with 8-stage
consumption
·
PWM circuit direct drive speaker or output by
transistor
·
20-pin SSOP (150mil/209mil) package
28-pin SOP (300mil) package
prescaler and one time base counter
Applications
·
Intelligent educational leisure products
·
Alert and warning systems
·
Sound effect generators
General Description
The HT83XXX is 8-bit high performance microcontroller
with voice synthesizer and tone generator. The
HT83XXX is designed for applications on multiple I/Os
with sound effects, such as voice and melody. It can pro-
vide various sampling rates and beats, tone levels, tem-
pos for speech synthesizer and melody generator.
The HT83XXX is excellent for versatile voice and sound
effect product applications. The efficient MCU instruc-
tions allow users to program the powerful custom appli-
cations. The system frequency of HT83XXX can be up
to 8MHz under 2.4V and include a HALT function to re-
duce power consumption.
Selection Table
Body
Voice ROM Size
Voice Length
HT83004
64K-bit
3 sec
HT83007
128K-bit
6 sec
HT83010
192K-bit
9 sec
HT83020
384K-bit
18 sec
HT83038
768K-bit
36 sec
HT83050
1024K-bit
48 sec
HT83074
1536K-bit
72 sec
Rev. 1.60
1
November 19, 2008
HT83XXX
Block Diagram
S T A C K 0
S T A C K 1
P ro g ra m
R O M
P ro g ra m
C o u n te r
S T A C K 2
S T A C K 3
IN T C
In te rru p t
C ir c u it
T M R 0
T M R 0 C
8 - s ta g e P r e s c a le r
S Y S C L K
8 - b it
T M R 1
In s tr u c tio n
R e g is te r
M P 0
M
U
X
T M R 1 C
8 - s ta g e P r e s c a le r
S Y S C L K
D a ta
M e m o ry
8 - b it
T im e B a s e
S Y S C L K /1 0 2 4
S Y S C L K /4
In s tr u c tio n
D e c o d e r
A L U
T im in g
G e n e r a tio n
M U X
P A C
P A
S T A T U S
P O R T A
P A 0 ~ P A 7
S h ifte r
P B C
P B
W D T S
P O R T B
P B 0 ~ P B 3
O S C 2
O S
R E
V D
V S
C 1
S
D
S
A C C
M
¸
2 5 6
U
W D T R C
O S C
X
S Y S C L K /4
W D T P r e s c a le r
S Y S C L K
P W M
P W M 1
P W M 2
Pin Assignment
N C
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
N C
N C
O S C 2
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
1 6
1 5
N C
N C
N C
P W M 2
P W M 1
V D D P
V D D
V S S P
V S S
O S C 1
O S C 2
R E S
N C
P B 3
1
2
3
4
5
6
7
8
9
1 0
2 0
1 9
1 8
1 7
1 6
1 5
1 4
1 3
1 2
1 1
R E S
P A 7
P A 6
P A 5
P A 4
P A 3
P A 2
P A 1
P A 0
N C
P A 0
P A 1
P A 2
P A 3
P A 4
P A 5
P A 6
P A 7
P B 0
P B 1
P B 2
O S C 1
V S S
V S S P
V D D
V D D P
P W M 1
P W M 2
N C
N C
H T 8 3 0 0 4 /H T 8 3 0 0 7 /H T 8 3 0 1 0 /H T 8 3 0 2 0
H T 8 3 0 3 8 /H T 8 3 0 5 0 /H T 8 3 0 7 4
2 0 S S O P -A
H T 8 3 0 0 4 /H T 8 3 0 0 7 /H T 8 3 0 1 0 /H T 8 3 0 2 0
H T 8 3 0 3 8 /H T 8 3 0 5 0 /H T 8 3 0 7 4
2 8 S O P -A
Rev. 1.60
2
November 19, 2008
HT83XXX
Pad Assignment
HT83004/HT83007/HT83010
P A 0
1
2
3
4
5
6
7
8
9
P A 1
P A 2
P A 3
P A 4
P A 5
P A 6
P A 7
2 1
2 0
1 9
1 8
1 7
1 6
1 5
1 0
1 1
P B 2
1 2
P B 3
1 3
R E S
1 4
P W M 2
P W M 1
V D D P
V D D
V S S P
V S S
O S C 1
O S C 2
(0 ,0 )
* The IC substrate should be connected to VSS in the PCB layout artwork.
HT83020/HT83038
P B 1
P B 0
Chip size: 2280´1475 (mm)
2
P A 0
P A 1
1
2
3
4
5
6
7
8
9
P A 2
P A 3
P A 4
P A 5
P A 6
P A 7
2 1
(0 ,0 )
2 0
1 9
1 8
1 7
1 6
1 0 1 1 1 2 1 3
R E S
1 5
1 4
P W M 2
P W M 1
V D D P
V D D
V S S P
V S S
O S C 1
O S C 2
* The IC substrate should be connected to
VSS
in the PCB layout artwork.
P B
P B
P B
P B
0
1
2
3
Chip size: 2180´1720 (mm)
2
Rev. 1.60
3
November 19, 2008
HT83XXX
HT83050/HT83074
P A 0
P A 1
2
3
4
5
6
7
8
9
P A 2
P A 3
P A 4
P A 5
P A 6
P A 7
1
(0 ,0 )
2 1
2 0
1 9
1 8
1 7
1 6
1 5
1 0 1 1 1 2 1 3
P B 3
P B 2
R E S
1 4
P W M 2
P W M 1
V D D P
V D D
V S S P
V S S
O S C 1
O S C 2
* The IC substrate should be connected to
VSS
in the PCB layout artwork.
P B 1
P B 0
Chip size: 2180´2075 (mm)
2
Pad Coordinates
HT83004/HT83007/HT83010
Pad No.
1
2
3
4
5
6
7
8
9
10
11
HT83020/HT83038
Pad No.
1
2
3
4
5
6
7
8
9
10
11
X
-940.400
-940.400
-940.400
-940.400
-940.400
-940.400
-940.400
-940.400
-947.200
-852.200
-749.200
Y
184.650
89.650
-13.350
-108.350
-211.350
-306.350
-409.350
-504.350
-710.400
-710.400
-710.400
Pad No.
12
13
14
15
16
17
18
19
20
21
X
-654.200
-551.200
940.400
940.400
940.600
940.600
896.250
904.900
904.900
904.900
Y
-710.400
-710.400
-693.700
-598.700
-491.000
-395.500
-285.750
-185.750
-66.200
144.300
X
-940.400
-940.400
-940.400
-940.400
-940.400
-940.400
-940.400
-940.400
-947.200
-852.200
-749.200
Y
307.150
212.150
109.150
14.150
-88.850
-183.850
-286.850
-381.850
-587.900
-587.900
-587.900
Pad No.
12
13
14
15
16
17
18
19
20
21
X
-654.200
-551.200
940.400
940.400
940.600
940.600
896.250
904.900
904.900
904.900
Y
-587.900
-587.900
-571.200
-476.200
-368.500
-273.000
-165.350
-63.250
56.300
266.800
Rev. 1.60
4
November 19, 2008
HT83XXX
HT83050/HT83074
Pad No.
1
2
3
4
5
6
7
8
9
10
11
X
-940.400
-940.400
-940.400
-940.400
-940.400
-940.400
-940.400
-940.400
-947.200
-852.200
-749.200
Y
7.150
-87.850
-190.850
-285.850
-388.850
-483.850
-586.850
-681.850
-887.900
-887.900
-887.900
Pad No.
12
13
14
15
16
17
18
19
20
21
X
-654.200
-551.200
940.400
940.400
940.600
940.600
896.250
904.900
904.900
904.900
Y
-887.900
-887.900
-871.200
-776.200
-668.500
-573.000
-463.250
-363.250
-243.700
-33.200
Pad Description
Pad Name
PA0~PA7
I/O
I/O
Mask Option
Wake-up,
Pull-high
or None
Pull-high
or None
¾
¾
¾
¾
¾
Description
Bidirectional 8-bit I/O port. Each bit can be configured as a wake-up input by
mask option. Software instructions determine the CMOS output or Schmitt trig-
ger input with or without pull-high resistor (mask option).
Bidirectional 4-bit I/O port. Software instructions determine the CMOS output or
Schmitt trigger input (pull-high resistor depending on mask option).
Negative power supply, ground
PWM negative power supply, ground
Positive power supply
PWM positive power supply, ground
Schmitt trigger reset input, active low
PB0~PB3
VSS
VSSP
VDD
VDDP
RES
OSC1,
OSC2
PWM1,
PWM2
I/O
¾
¾
¾
¾
I
¾
OSC1 and OSC2 are connected to an RC network or crystal (by mask option)
for the internal system clock. In the case of RC operation, OSC2 is the output
RC or Crystal
terminal for 1/4 system clock. The system clock may came form the crystal, the
two pins cannot be floating.
¾
PWM output for driving a external transistor or speaker
O
Absolute Maximum Ratings
Supply Voltage ..........................V
SS
+2.4V to V
SS
+5.5V
Input Voltage .............................V
SS
-0
.
3V to V
DD
+0.3V
Storage Temperature ...........................-50°C to 125°C
Operating Temperature ..........................-40°C to 85°C
Note: These are stress ratings only. Stresses exceeding the range specified under
²Absolute
Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Rev. 1.60
5
November 19, 2008
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