TIGER ELECTRONIC CO.,LTD
DS1307
64 X 8 Serial Real Time Clock
FEATURES
Real time clock counts seconds, minutes,
hours, date of the month, month, day of the
week, and year with leap year compensation
valid up to 2100
56 byte nonvolatile RAM for data storage
2-wire serial interface
Programmable squarewave output signal
Automatic power-fail detect and switch
circuitry
Consumes less than 500 nA in battery backup
mode with oscillator running
Optional industrial temperature range
-40°C to +85°C
Available in 8-pin DIP or SOIC
Recognized by Underwriters Laboratory
PIN ASSIGNMENT
X1
X2
V
BAT
GND
l
2
3
4
8
7
6
5
V
CC
SQW/OUT
SCL
SDA
DS1307 8-Pin DIP (300 mil)
X1
X2
V
BAT
GND
l
2
3
4
8
7
6
5
V
CC
SQW/OUT
SCL
SDA
DS1307Z 8-Pin SOIC (150 mil)
PIN DESCRIPTION
V
CC
X1, X2
V
BAT
GND
SDA
SCL
SQW/OUT
- Primary Power Supply
- 32.768 kHz Crystal Connection
- +3V Battery Input
- Ground
- Serial Data
- Serial Clock
- Square wave/Output Driver
ORDERING INFORMATION
DS1307
DS1307Z
DS1307N
DS1307ZN
8-Pin DIP
8-Pin SOIC (150 mil)
8-Pin DIP (Industrial)
8-Pin SOIC (Industrial)
DESCRIPTION
The DS1307 Serial Real Time Clock is a low power, full BCD clock/calendar plus 56 bytes of
nonvolatile SRAM. Address and data are transferred serially via a 2-wire bi-directional bus. The
clock/calendar provides seconds, minutes, hours, day, date, month, and year information. The end of the
month date is automatically adjusted for months with less than 31 days, including corrections for leap
year. The clock operates in either the 24-hour or 12-hour format with AM/PM indicator. The DS1307
has a built-in power sense circuit which detects power failures and automatically switches to the battery
supply.
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081800
DS1307
OPERATION
The DS1307 operates as a slave device on the serial bus. Access is obtained by implementing a START
condition and providing a device identification code followed by a register address. Subsequent registers
can be accessed sequentially until a STOP condition is executed. When V
CC
falls below 1.25 x V
BAT
the
device terminates an access in progress and resets the device address counter. Inputs to the device will
not be recognized at this time to prevent erroneous data from being written to the device from an out of
tolerance system. When V
CC
falls below V
BAT
the device switches into a low current battery backup
mode. Upon power up, the device switches from battery to V
CC
when V
CC
is greater than V
BAT
+0.2V and
recognizes inputs when V
CC
is greater than 1.25 x V
BAT
. The block diagram in Figure 1 shows the main
elements of the Serial Real Time Clock.
DS1307 BLOCK DIAGRAM
Figure 1
SIGNAL DESCRIPTIONS
V
CC
, GND -
DC power is provided to the device on these pins. V
CC
is the +5 volt input. When 5 volts is
applied within normal limits, the device is fully accessible and data can be written and read. When a
3-volt battery is connected to the device and V
CC
is below 1.25 x V
BAT
, reads and writes are inhibited.
However, the Timekeeping function continues unaffected by the lower input voltage. As V
CC
falls below
V
BAT
the RAM and timekeeper are switched over to the external power supply (nominal 3.0V DC) at
V
BAT
.
V
BAT
- Battery input for any standard 3-volt lithium cell or other energy source. Battery voltage must be
held between 2.0 and 3.5 volts for proper operation. The nominal write protect trip point voltage at which
access to the real time clock and user RAM is denied is set by the internal circuitry as 1.25 x V
BAT
nominal. A lithium battery with 48 mAhr or greater will back up the DS1307 for more than 10 years in
the absence of power at 25 degrees C.
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DS1307
SCL (Serial Clock Input)
- SCL is used to synchronize data movement on the serial interface.
SDA (Serial Data Input/Output) -
SDA is the input/output pin for the 2-wire serial interface. The SDA
pin is open drain which requires an external pullup resistor.
SQW/OUT (Square Wave/ Output Driver) -
When enabled, the SQWE bit set to 1, the SQW/OUT pin
outputs one of four square wave frequencies (1 Hz, 4 kHz, 8 kHz, 32 kHz). The SQW/OUT pin is open
drain which requires an external pullup resistor. SQW/OUT will operate with either Vcc or Vbat applied.
X1, X2
- Connections for a standard 32.768 kHz quartz crystal. The internal oscillator circuitry is
designed for operation with a crystal having a specified load capacitance (CL) of 12.5 pF.
For more information on crystal selection and crystal layout considerations, please consult Application
Note 58, “Crystal Considerations with Dallas Real Time Clocks.” The DS1307 can also be driven by an
external 32.768 kHz oscillator. In this configuration, the X1 pin is connected to the external oscillator
signal and the X2 pin is floated.
Please review Application Note 95, “Interfacing the DS1307 with a 8051-Compatible Microcontroller”
for additional information.
RTC AND RAM ADDRESS MAP
The address map for the RTC and RAM registers of the DS1307 is shown in Figure 2. The real time
clock registers are located in address locations 00h to 07h. The RAM registers are located in address
locations 08h to 3Fh. During a multi-byte access, when the address pointer reaches 3Fh, the end of RAM
space, it wraps around to location 00h, the beginning of the clock space.
DS1307 ADDRESS MAP
Figure 2
00H
SECONDS
MINUTES
HOURS
DAY
DATE
MONTH
YEAR
07H
08H
3FH
CONTROL
RAM
56 x 8
CLOCK AND CALENDAR
The time and calendar information is obtained by reading the appropriate register bytes. The real time
clock registers are illustrated in Figure 3. The time and calendar are set or initialized by writing the
appropriate register bytes. The contents of the time and calendar registers are in the Binary-Coded
Decimal (BCD) format. Bit 7 of Register 0 is the Clock Halt (CH) bit. When this bit is set to a 1, the
oscillator is disabled. When cleared to a 0, the oscillator is enabled.
Please note that the initial power on state of all registers is not defined. Therefore it is important to
enable the oscillator (CH bit=0) during initial configuration.
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DS1307
The DS1307 can be run in either 12-hour or 24-hour mode. Bit 6 of the hours register is defined as the
12- or 24-hour mode select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is
the AM/PM bit with logic high being PM. In the 24-hour mode, bit 5 is the second 10 hour bit (20-
23 hours).
On a 2-wire START, the current time is transferred to a second set of registers. The time information is
read from these secondary registers, while the clock may continue to run. This eliminates the need to re-
read the registers in case of an update of the main registers during a read.
DS1307 TIMEKEEPER REGISTERS
Figure 3
CONTROL REGISTER
The DS1307 Control Register is used to control the operation of the SQW/OUT pin.
BIT 7
OUT
BIT 6
X
BIT 5
X
BIT 4
SQWE
BIT 3
X
BIT 2
X
BIT 1
RS1
BIT 0
RS0
OUT (Output control): This bit controls the output level of the SQW/OUT pin when the square wave
output is disabled. If SQWE=0, the logic level on the SQW/OUT pin is 1 if OUT=1 and is 0 if OUT=0.
SQWE (Square Wave Enable): This bit, when set to a logic 1, will enable the oscillator output. The
frequency of the square wave output depends upon the value of the RS0 and RS1 bits.
RS (Rate Select): These bits control the frequency of the square wave output when the square wave
output has been enabled. Table 1 lists the square wave frequencies that can be selected with the RS bits.
SQUAREWAVE OUTPUT FREQUENCY
Table 1
RS1
0
0
1
1
RS0
0
1
0
1
SQW OUTPUT
FREQUENCY
1 Hz
4.096 kHz
8.192 kHz
32.768 kHz
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DS1307
2-WIRE SERIAL DATA BUS
The DS1307 supports a bi-directional 2-wire bus and data transmission protocol. A device that sends
data onto the bus is defined as a transmitter and a device receiving data as a receiver. The device that
controls the message is called a master. The devices that are controlled by the master are referred to as
slaves. The bus must be controlled by a master device which generates the serial clock (SCL), controls
the bus access, and generates the START and STOP conditions. The DS1307 operates as a slave on the
2-wire bus. A typical bus configuration using this 2-wire protocol is show in Figure 4.
TYPICAL 2-WIRE BUS CONFIGURATION
Figure 4
Figures 5, 6, and 7 detail how data is transferred on the 2-wire bus.
Data transfer may be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in
the data line while the clock line is high will be interpreted as control signals.
Accordingly, the following bus conditions have been defined:
Bus not busy:
Both data and clock lines remain HIGH.
Start data transfer:
A change in the state of the data line, from HIGH to LOW, while the clock is HIGH,
defines a START condition.
Stop data transfer:
A change in the state of the data line, from LOW to HIGH, while the clock line is
HIGH, defines the STOP condition.
Data valid:
The state of the data line represents valid data when, after a START condition, the data line
is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed
during the LOW period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a START condition and terminated with a STOP condition. The
number of data bytes transferred between START and STOP conditions is not limited, and is determined
by the master device. The information is transferred byte-wise and each receiver acknowledges with a
ninth bit. Within the 2-wire bus specifications a regular mode (100 kHz clock rate) and a fast mode
(400 kHz clock rate) are defined. The DS1307 operates in the regular mode (100 kHz) only.
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