TS68230
HMOS PARALLEL INTERFACE/TIMER
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TS68000 BUS COMPATIBLE
PORT MODES INCLUDE :
BIT I/O
UNIDIRECTIONAL 8 BIT AND 16 BIT
BIDIRECTIONAL 8 BIT AND 16 BIT
PROGRAMMABLE HANDSHAKING OPTIONS
24-BIT PROGRAMMABLE TIMER MODES
FIVE SEPARATE INTERRUPT VECTORS
SEPARATE PORT AND TIMER INTERRUPT
SERVICE REQUESTS
REGISTERS ARE READ/WRITE AND DIRECT-
LY ADDRESSABLE
REGISTERS ARE ADDRESSED FOR MOVEP
(Move Peripheral) AND DMAC COMPATIBILITY
1
P
(PDIP48)
FN
(PLCC52)
PIN CONNECTIONS
DESCRIPTION
The TS68230 parallel interface/timer (PI/T) provides
versatile double buffered parallel interfaces and a
system oriented timer for TS68000 systems. The pa-
rallel interfaces operate in unidirectional or bidirectio-
nal modes, either 8 or 16 bits wide. In the
unidirectional modes, an associated data direction
register determines whether each port pin is an input
or output. In the bidirectional modes the data direc-
tion registers are ignored and the direction is deter-
mined dynamically by the state of four handshake
pins. These programmable handshake pins provide
an interface flexible enough for connection to a wide
variety of low, medium, or high speed peripherals or
other computer systems. The PI/T ports allow use of
vectored or auto-vectored interrupts, and also pro-
vide a DMA request pin for connection to the 68440
direct memory access controller (DMAC) or a similar
circuit. The PI/T timer contains a 24-bit wide counter
and a 5-bit prescaler. The timer may be clocked by
the system clock (PI/T CLK pin) or by an external
clock (TIN pin), and a 5-bit prescaler can be used. It
can generate periodic interrupts, a square wave, or
a single interrupt after a programmed time period. It
can also be used for elapsed time measurement or
as a device watchdog.
January 1989
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TS68230
SECTION 1
INTRODUCTION
The TS68230 parallel interface/timer (PI/T) provides
versatile double buffered parallel interfaces and a
system oriented timer for TS68000 systems. The
parallel interfaces operate in unidirectional or bidi-
rectional modes, either 8 or 16 bits wide. In the uni-
directional modes, an associated data direction
register determines whether each port pin is an input
or output. In the bidirectional modes the data direc-
tion registers are ignored and the direction is deter-
mined dynamically by the state of four handshake
pins. These programmable handshake pins provide
an interface flexible enough for connection to a wide
variety of low, medium, or high speed peripherals or
other computer systems. The PI/T ports allow use
of vectored or autovectored interrupts, and also pro-
vide a DMA request pin for connection to the 68440
direct memory access controller (DMAC) or a similar
circuit. The PI/T timer contains a 24-bit wide counter
and a 5-bit prescaler. The timer may be clocked by
the system clock (PI/T CLK pin) or by an external
clock (TIN pin), and a 5-bit prescaler can be used.
It can generate periodic interrupts, a square wave,
or a single interrupt after a programmed time period.
It can also be used for elapsed time measurement
or as a device watchdog.
The PI/T consists of two logically independent sec-
tions : the ports and the timer. The port section
consists of port A (PA0-PA7), port B (PB0-PB7), four
handshake pins (H1, H2, H3, and H4), two general
input/output (I/O) pins, and six dual-function pins.
The dual-function pins can individually operate as a
third port (port C) or an alternate function related to
either port A, port B, or the timer. The four program-
mable handshake pins, depending on the mode,
can control data transfer to and from the ports, or
can be used as interrupt generating inputs or I/O
pins. Refer to figure 1.1.
The timer consists of a 24-bit counter, optionally
clocked by a 5-bit prescaler. Three pins provide
complete timer I/O : PC2/TIN, PC3/TOUT, and
PC7/TIACK. Only the ones needed for the given
configuration perform the timer function, while the o-
thers remain port C I/O.
The system bus interface provides for asynchro-
nous transfer of data from the PI/T to a bus master
over the data bus (D0-D7). Data transfer acknow-
ledge (DTACK), register selects (RS1-RS5), timer
interrupt acknowledge (TIACK), read/write line
(R/W), chip select (CS), or port interrupt acknow-
ledge (PIACK) control data transfer between the
PI/T and an TS68000.
1.1. PORT MODE DESCRIPTION
The primary focus of most applications will be on
port A, port B, the handshake pins, the port interrupt
pins, and the DMA request pin. They are controlled
in the following way : the port general control register
contains a 2-bit field that specifies one of four ope-
ration modes. These govern the overall operation of
the ports and determine their interrelation-ships.
Some modes require additional information from
each port’s control register to further define its ope-
ration. In each port control register, there is a 2-bit
submode field that serves this purpose. Each port
mode/submode combination specifies a set of pro-
grammable characteristics that fully define the be-
havior of that port and two of the handshake pins.
This structure is summarized in table 1.1 and fig-
ure 1.2.
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Features of the PI/T include :
TS68000 Bus Compatible
Port Modes Include :
Bit I/O
Unidirectional 8 Bit and 16 Bit
Bidirectional 8 Bit and 16 Bit
Programmable Handshaking Options
24-Bit Programmable Timer Modes
Five Separate Interrupt Vectors
Separate Port and Timer Interrupt Service
Requests
Registers are Read/Write and Directly
Addressable
Registers are Addressed for MOVEP (Move
Peripheral) and DMAC Compatibility
2/61
TS68230
Table 1.1 :
Port Mode Control Summary.
Mode 0
(unidirectional 8-bit mode)
Port A
Submode 00 - Pin-definable Double-buffered Input or Single-buffered Output
H1 - Latches Input Data
H2 - Status/interrupt Generating Input, General-purpose Output, or Operation with H1 in the Interlocked or
Pulsed Handshake Protocols
Submode 01 - Pin-definable Double-buffered Output or Non-latched Input
H1 - Indicates Data Received by Peripheral
H2 - Status/interrupt Generating Input, General-purpose Output, or Operation with H1 in the Interlocked or
Pulsed Handshake Protocols
Submode 1X - Pin-definable Single-buffered Output or non-latched Input
H1 - Status/interrupt Generating Input
H2 - Status/interrupt Generating Input or General-purpose Output
Port B
H3 and H4 - Identical to Port A, H1 and H2
Mode 1
(unidirectional 16-bit mode)
Port A - Most-significant Data Byte or non-latched Input or Single-buffered Output
Submode XX - (not used)
H1 - Status/interrupt Generating Input
H2 - Status/interrupt Generating Input or General-purpose Output
Port B - Least-significant Data Byte
Submode X0 - Pin-definable Double-buffered Input or Single-buffered Output
H3 - Latches Input Data
H4 - Status/interrupt Generating Input, General-purpose Output, or Operation with H3 in the Interlocked or
pulsed handshake Protocols
Submode X1 - Pin-definable Double-buffered Output or Non-latched Input
H3 - Indicates Data Received by Peripheral
H4 - Status/interrupt Generating Input, General-purpose Output, or Operation with H3 in the Interlocked or
Pulsed Hanshake Protocols
Mode 2
(bidirectional 8-bit mode)
Port A - Bit I/O
Submode XX - (not used)
Port B - Double-buffered Bidirectional Data
Submode XX - (not used)
H1 - Indicates Output Data Received by the Peripheral and Controls Output Drivers
H2 - Operation with H1 in the Interlocked or Pulsed Output Handshake Protocols
H3 - Latches Input Data
H4 - Operation with H3 in the Interlocked or Pulsed Input Handshake Protocols
Mode 3
(bidirectional 16-bit mode)
Port A - Double-buffered Bidirectional Data (most-signifiant data byte)
Submode XX - (not used)
Port B - Double-buffered Bidirectional Data (least-signifiant data byte)
Submode XX - (not used)
H1 - Indicates Output Data Received by the Peripheral and Controls Output Drivers
H2 - Operation with H1 in the Interlocked or Pulsed Output Handshake Protocols
H3 - Latches Input Data
H4 - Operation with H3 in the Interlocked or Pulsed Input Handshake Protocols
4/61
FPGA/CPLD
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