TS652
DIFFERENTIAL VARIABLE GAIN AMPLIFIER
s
LOW NOISE :
4.6nV/√Hz
s
LOW DISTORTION
s
HIGH SLEW RATE :
90V/µs
s
WIDE BANDWIDTH : 52MHz @ -3dB &
18dB gain
s
GAIN PROGRAMMABLE from -9dB to +30dB
with 3dB STEPS
s
POWER DOWN FUNCTION
DESCRIPTION
The TS652 is a differential digitally controled vari-
able gain amplifier featuring a high slew rate of
90V/µs, a large bandwidth, a very low distortion
and a very low current and voltage noise.
The gain can be set from -9dB to +30dB through a
4bit digital word, with 3dB steps.
The gain monotonicity is guaranteed by design.
D
SO-14
(Plastic Micropackage)
This device is particularly intended for applications
such as preamplification in telecommunication
systems using multiple carriers.
APPLICATION
s
Preamplifier and automatic gain control for
Assymetric Digital Subscriber Line (ADSL).
ORDER CODE
Gain Control
Logic Decoder
O
so
b
TS652ID
te
le
ro
P
uc
d
s)
t(
so
b
-O
PIN CONNECTIONS
(top view)
P
te
le
od
r
c
u
s)
t(
+Vcc1 1
14 +Vcc2
Input 1 2
Input 2 3
4
5
13 Output 1
12 Output 2
11 Power Down
10 -Vcc
9 AGND
8 DGND
LSB
GC1
GC2
Package
Temperature Range
D
-40, +85°C
•
Part Number
GC3 6
7
MSB
GC4
D =
Small Outline Package (SO) - also available in Tape & Reel (DT)
October 2001
1/9
TS652
ABSOLUTE MAXIMUM RATINGS
Symbol
V
CC
V
i
T
oper
T
std
T
j
R
thjc
R
thja
Supply voltage
1)
Input Voltage
2)
Operating Free Air Temperature Range TS652ID
Storage Temperature
Maximum Junction Temperature
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambiante Area
Output Short Circuit Duration
1. All voltages values are with respect to network terminal.
2. The magnitude of input and output voltages must never exceed V
CC
+0.3V.
Parameter
Value
14
0 to 14
-40 to + 85
-65 to +150
150
22
125
Infinite
Unit
V
V
°C
°C
°C
°C/W
°C/W
OPERATING CONDITIONS
Symbol
V
CC
V
icm
Supply Voltage
Common Mode Input Voltage
Parameter
Value
5 to 12
V
CC
/2
O
so
b
te
le
ro
P
uc
d
s)
t(
so
b
-O
P
te
le
od
r
c
u
s)
t(
V
V
Unit
2/9
TS652
ELECTRICAL CHARACTERISTICS.
V
CC
=
±
6Volts, T
amb
= 25°C (unless otherwise specified).
Symbol
V
i
I
CC
∆V
OFFSET
SVR
V
pdw
I
ccpdw
Z
out
Z
in
V
OH
V
OL
A
V
P
AV
A
vstep
A
vmin
Parameter
Voltage on the Input Pin
Total Supply Current
Differential Input Offset Voltage
Supply Voltage Rejection Ratio
Thershold Voltage for Power
Down Mode (high level active)
Power Down Total Consumption
Power Down Output Impedance
Test Condition
Min.
Typ.
0
28
6
50
80
0
3.3
150kΩ//5pF
100kΩ//5pF
4
4.5
-4.5
-9
-1
2.4
-4
V
0.8
150
100kΩ
Max
Unit
V
mA
mV
dB
V
V
µA
DC PERFORMANCE
No load, V
out
= 0
V
in
= 0, A
V
= 30dB
A
V
= 0dB
Low Level
High Level
Power Down Mode
Power Down Mode
POWER DOWN MODE
2
AC PERFORMANCE
Input Impedance
High Level Output Voltage
R
L
= 500Ω
R
L
connected to GND
Low Level Output Voltage
R
L
= 500Ω
R
L
connected to GND
Voltage Gain
F= 1MHz
Gain monotonicity guaranteed by design
Precision of the Voltage Gain
F= 1MHz
Step Value
F= 1MHz
Gain Mismatch between Both
F= 1MHz
Channels
A
V
= -9dB
Bandwidth @ -3dB
A
V
= 0dB
R
L
= 500Ω
A
V
= +18dB
C
L
= 15pF
A
V
= +30dB
A
V
= +30dB, F = 1MHz
Bandwidth Roll-off
|Source|
Bandwidth @ -3dB
R
L
= 500Ω, C
L
= 15pF
Sink
V
o
= 2Vpeak
Slew Rate (gain independent)
Equivalent Input Noise Current
B
w
R
bw
I
o
SR
in
en
NOISE AND DISTORTION
Equivalent Input Noise Voltage
THD30
O
so
b
IM3
et
l
Harmonic Distorsion
P
e
d
ro
ct
u
s)
(
so
b
-O
P
te
le
55
32
26
10
17
17
50
od
r
3
110
69
52
18
0.08
28
22
100
1.5
4.6
c
u
1
3.6
1
200
132
100
36
30
s)
t(
V
dB
dB
dB
dB
MHz
dB
mA
V/µs
pA/√Hz
nV/√Hz
Third Order Intermodulation
Product
F1 = 180kHz, F2 = 280kHz
IM3
Third Order Intermodulation
Product
F1 = 70kHz, F2 = 80kHz
F = 100kHz
F = 100kHz
A
V
= 30dB
1Vpeak, F = 150kHz,
A
V
= +30dB, R
L
= 500Ω//15pF
H2
H3
H4
H5
V
out
= 1Vpeak, A
V
= +30dB
R
L
= 500Ω//15pF
@ 80kHz
@ 380kHz
@640kHz
@740kHz
V
out
= 1Vpeak, A
V
= +30dB
R
L
= 500Ω//15pF
@ 60kHz
@ 90kHz
@220kHz
@230kHz
-70
-93
-98
-99
dBc
-77
-85
-86
-87
dBc
-77
-79
-83
-84
dBc
3/9
TS652
DIGITAL INPUTS
Symbol
GC1, GC2, GC3
and GC4
Parameter
Low Level
High Level
2
Min.
Typ.
0
3.3
Max.
0.8
Unit
V
SIMPLIFIED SCHEMATIC
The TS652 consists of two independent channels.
Each channel has two stages. The first is a very low noise digitally controlled variable gain amplifier (range
0 to 18dB).
The TS652 features a high input impedance and a low noise current. To minimize the overall noise figure,
the source impedance must be less than 3kΩ.
This value gives an equal contribution of voltage and current noises.
The second stage is a gain/attenuation stage (+12dB to -9dB) featuring a low output impedance.
This output stage can drive loads as low as 500Ω.
v
Input1
+
_
_
Ouput1
+
+Vcc1
v
-Vcc
Analog GND
(AGND)
v
+
Input2
_
POWER DOWN MODE POSITION
O
so
b
te
le
ro
P
uc
d
Power
Down
s)
t(
+Vcc
GAIN CONTROL
LOGIC DECODER
so
b
-O
+
_
Ouput2
+Vcc2
P
te
le
od
r
c
u
s)
t(
v
v
GC1
GC2
GC3
GC4
Digital GND
(DGND)
+Vcc
Power Down
Input
Output
-Vcc
-Vcc
4/9
TS652
BANDWIDTH
The small signal bandwidth is almost constant for gains between +18dB to 0dB and is in the order of
52MHz to 70MHz respectively. For 30dB gain the bandwidth is around 18MHz.
The power bandwidth is typically equal to 30MHz for 2V peak to peak signals.
MAXIMUM INPUT LEVEL
The input level must not exceed the following values :
negative peak value: must be greater than -V
CC
+ 1.5V
positive peak value: must be less than +V
CC
- 1.5V
For example, if a
±
6V power supply is used, the input signal can swing between -4.5V and +4.5V.
These values are due to common mode input range limitations of the input stage of the first amplifier.
Some other limitations may occur, due to the slew rate of the first operational amplifier (typically in the or-
der of 300V/µs). This means that the maximum input signal decreases at high frequency.
SINGLE SUPPLY OPERATION
The incoming signal is AC coupled to the inputs.
The TS652 can be used either with a dual or a single supply. If a single supply is used, the inputs are bi-
ased to the mid supply voltage (+V
CC/2
). This bias network must be carefully designed, in order to reject
any noise present on the supply rail.
The AGND pin (9) must be connected to +V
CC/2
. The bias current of the second stage (inverting structure)
is 8µA for both amplifiers. A resistor divider structure can be used. Two resistances should be chosen by
considering 8µA as the 1% of the total current through these resistances. For a single +12V supply volt-
age, two resistances of 7.5kΩ can be used. The differential input consists of a high pass circuit, formed by
the 1µF capacitor and a 1kΩ resistance and gives a break frequency of 160Hz.
SINGLE +12V SUPPLY OF THE TS652
1µF
IN+
O
so
b
te
le
1k
1k
ro
P
47k
47k
uc
d
s)
t(
10nF
so
b
-O
TS652
P
te
le
od
r
c
u
s)
t(
100nF
12V
+Vcc1 1
Input 1
14 +Vcc2
13 Output 1
12
Output 2
12V
2
10nF
100nF
10µF
Input 2 3
10nF
1µF
GC1 4
Gain Control
Logic Decoder
GC2 5
11 Power Down
10 -Vcc
12V
7.5k
IN-
GC3 6
9
AGND
1µF
GC4 7
8 DGND
10nF
7.5k
1µF
5/9
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