FemtoClock
®
Crystal-to-CML Clock Generator
Datasheet
845252
General Description
The 845252 is a 3.3V/2.5V CML clock generator designed for
Ethernet applications. The device synthesizes either a 50MHz,
62.5MHz, 100MHz, 125MHz, 156.25MHz, 250MHz or 312.5MHz
clock signal with excellent phase jitter performance. The clock signal
is distributed to two low-skew differential CML outputs. The device is
suitable for driving the reference clocks of Ethernet PHYs. The
device supports 3.3V and 2.5V voltage supply and is packaged in a
small, lead-free (RoHS 6) 32-lead VFQFN package. The extended
temperature range supports telecommunication, wireless
infrastructure and networking end equipment requirements. The
device is a member of the family of High Performance Clock
Solutions from IDT.
Features
•
•
•
•
Clock generation of: 50MHz, 62.5MHz, 100MHz, 125MHz,
156.25MHz, 250MHz and 312.5MHz
Two differential CML clock output pairs
Crystal interface designed for 25MHz,
18pF parallel resonant crystal
RMS phase jitter @ 125MHz, using a 25MHz crystal
(1.875MHz – 20MHz): 400fs (typical), 3.3V
Offset
Noise Power
100Hz.................... -102.4 dBc/Hz
1kHz.................... -119.4 dBc/Hz
10kHz................... -124.8 dBc/Hz
100kHz................... -125.7 dBc/Hz
•
•
•
•
•
LVCMOS interface levels for the control inputs
Full 3.3V and 2.5V supply voltage
Available in lead-free (RoHS 6) 32 VFQFN package
-40°C to 85°C ambient operating temperature
For functional replacement part use 8T49N241
Block Diagram
XTAL_IN
OSC
XTAL_OUT
f
REF
0
0
Pin Assignment
GND
nQ1
Q1
FBSEL
nc
REF_CLK
REF_SEL
FBSEL
nBYPASS
FSEL1:0
nOE
Pulldown
Pulldown
Pulldown
Pullup
Pulldown, Pulldown
Pulldown
Phase
Detector
1
VCO
490-680
MHz
1
÷2
(default),
÷4,
÷5,
÷10
Q0
nQ0
nQ0
1
2
3
4
5
6
7
8
32 31 30 29 28 27 26 25
24
23
22
21
20
19
18
17
9
nc
nc
nc
nc
nc
nc
REF_SEL
FSEL1
FSEL0
nc
V
DD
nc
Q1
nQ1
Q0
V
DD
nOE
nc
nc
nc
nc
÷20,
÷25
(default)
10 11 12 13 14 15 16
XTAL_OUT
nBYPASS
REF_CLK
XTAL_IN
V
DDA
GND
nc
845252
32 lead VFQFN
5.0mm x 5.0mm x 0.925mm package body
K Package
Top View
©2016 Integrated Device Technology, Inc.
1
Revision B, November 11, 2016
845252 Datasheet
Table 1. Pin Descriptions
Number
1, 2
3, 18
4
5, 6, 7, 8, 9, 16,
17, 19, 23, 24,
25, 30, 31, 32
10
11
12
13, 29
14,
15
20, 21
22
26
27, 28
Name
nQ0, Q0
V
DD
nOE
Output
Power
Input
Pulldown
Type
Description
Differential clock output pair. CML interface levels.
Core supply pins.
Output enable pin. See Table 3E for function.
LVCMOS/LVTTL interface levels.
Do not connect.
Analog supply pin.
Pullup
Pulldown
PLL bypass pin. See Table 3D for function.
LVCMOS/LVTTL interface levels.
Single-ended reference clock input. LVCMOS/LVTTL interface levels.
Power supply ground.
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
Pulldown
Pulldown
Pulldown
Output frequency divider select enable pins. See Table 3C for function.
LVCMOS/LVTTL interface levels.
PLL reference clock select pin. See Table 3A for function.
LVCMOS/LVTTL interface levels.
PLL feedback divider select pin. See Table 3B for function.
LVCMOS/LVTTL interface levels.
Differential clock output pair. CML interface levels.
nc
V
DDA
nBYPASS
REF_CLK
GND
XTAL_OUT,
XTAL_IN
FSEL0, FSEL1
REF_SEL
FBSEL
nQ1, Q1
Unused
Power
Input
Input
Power
Input
Input
Input
Input
Output
NOTE:
Pulldown
and
Pullup
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLDOWN
R
PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
©2016 Integrated Device Technology, Inc.
2
Revision B, November 11, 2016
845252 Datasheet
Function Tables
Table 3A. PLL Reference Clock Select Function Table
Input
REF_SEL
0 (default)
1
Operation
The crystal interface is the selected.
The REF_CLK input is the selected.
NOTE: REF_SEL is an asynchronous control.
Table 3B. PLL Feedback Select Function Table
Input
FBSEL
0 (default)
1
Operation
f
VCO
= f
REF
* 25
f
VCO
= f
REF
* 20
NOTE: FBSEL is an asynchronous control.
Table 3C. Output Divider Select Function Table
Input
FSEL1
0 (default)
0
1
1
FSEL0
0 (default)
1
0
1
Operation
f
OUT
= f
VCO
÷ 2
f
OUT
= f
VCO
÷ 4
f
OUT
= f
VCO
÷ 5
f
OUT
= f
VCO
÷ 10
Output Frequency f
OUT
with f
REF
= 25MHz
FBSEL = 0
312.5MHz
156.25MHz
125MHz
62.5MHz
FBSEL = 1
250MHz
125MHz
100MHz
50MHz
NOTE: FSEL[1:0] are asynchronous controls.
Table 3D. PLL nBYPASS Function Table
Input
nBYPASS
0
1 (default)
Operation
PLL is bypassed. The reference frequency f
REF
is divided by the selected
output divider. AC specifications do not apply in PLL bypass mode.
PLL is enabled. The reference frequency f
REF
is multiplied by the selected
feedback divider and then divided by the selected output divider.
NOTE: nBYPASS is an asynchronous control.
Table 3E. Output Enable Function Table
Input
nOE
0 (default)
1
Operation
Outputs enabled.
Outputs disabled (high-impedance).
NOTE: nOE is an asynchronous control.
©2016 Integrated Device Technology, Inc.
3
Revision B, November 11, 2016
845252 Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
43.4°C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= 3.3V±5%, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDA
I
DD
I
DDA
Parameter
Core Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
V
DD
– 0.12
Typical
3.3
3.3
Maximum
3.465
V
DD
88
12
Units
V
V
mA
mA
Table 4B. Power Supply DC Characteristics,
V
DD
= 2.5V±5%, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDA
I
DD
I
DDA
Parameter
Core Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
2.375
V
DD
– 0.11
Typical
2.5
2.5
Maximum
2.625
V
DD
84
11
Units
V
V
mA
mA
©2016 Integrated Device Technology, Inc.
4
Revision B, November 11, 2016
845252 Datasheet
Table 4C. LVCMOS/LVTTL Input DC Characteristics,
V
DD
= 3.3V±5% or 2.5V±5%, T
A
= -40°C to 85°C
Symbol
V
IH
Parameter
Input High Voltage
Test Conditions
Minimum
2
1.7
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.7
150
5
-5
-150
Units
V
V
V
V
µA
µA
µA
µA
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V or 2.625V,
V
IN
= 0V
V
DD
= 3.465V or 2.625V,
V
IN
= 0V
V
IL
Input Low Voltage
FBSEL, nOE, FSEL[1:0],
REF_SEL, REF_CLK
nBYPASS
FBSEL, nOE, FSEL[1:0],
REF_SEL, REF_CLK
nBYPASS
I
IH
Input
High Current
I
IL
Input
Low Current
Table 4D. CML DC Characteristics,
V
DD
= 3.3V±5% or 2.5V±5%, T
A
= -40°C to 85°C
Symbol
V
OH
V
OUT
Parameter
Output High Voltage
Output Voltage Swing
Test Conditions
Minimum
V
DD
- 0.02
325
650
Typical
V
DD
- 0.01
400
800
Maximum
V
DD
600
1200
Units
V
mV
mV
V
DIFF_OUT
Differential Output Voltage Swing
Table 5. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Test Conditions
Minimum
Typical
Fundamental
25
50
7
MHz
Maximum
Units
pF
©2016 Integrated Device Technology, Inc.
5
Revision B, November 11, 2016
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