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PHB37N06LT/T3

Description
TRANSISTOR 37 A, 55 V, 0.035 ohm, N-CHANNEL, Si, POWER, MOSFET, FET General Purpose Power
CategoryDiscrete semiconductor    The transistor   
File Size116KB,12 Pages
ManufacturerNXP
Websitehttps://www.nxp.com
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PHB37N06LT/T3 Overview

TRANSISTOR 37 A, 55 V, 0.035 ohm, N-CHANNEL, Si, POWER, MOSFET, FET General Purpose Power

PHB37N06LT/T3 Parametric

Parameter NameAttribute value
MakerNXP
package instructionSMALL OUTLINE, R-PSSO-G2
Reach Compliance Codeunknown
ECCN codeEAR99
Avalanche Energy Efficiency Rating (Eas)45 mJ
Shell connectionDRAIN
ConfigurationSINGLE WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage55 V
Maximum drain current (ID)37 A
Maximum drain-source on-resistance0.035 Ω
FET technologyMETAL-OXIDE SEMICONDUCTOR
Maximum feedback capacitance (Crss)150 pF
JESD-30 codeR-PSSO-G2
Number of components1
Number of terminals2
Operating modeENHANCEMENT MODE
Maximum operating temperature175 °C
Package body materialPLASTIC/EPOXY
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Polarity/channel typeN-CHANNEL
Maximum power consumption environment100 W
Maximum pulsed drain current (IDM)148 A
Certification statusNot Qualified
surface mountYES
Terminal formGULL WING
Terminal locationSINGLE
transistor applicationsSWITCHING
Transistor component materialsSILICON
Maximum off time (toff)145 ns
Maximum opening time (tons)131 ns
Philips Semiconductors
Product specification
TrenchMOS™ transistor
Logic level FET
FEATURES
’Trench’
technology
• Very low on-state resistance
• Fast switching
• Stable off-state characteristics
• High thermal cycling performance
• Low thermal resistance
PHP37N06LT, PHB37N06LT, PHD37N06LT
SYMBOL
d
QUICK REFERENCE DATA
V
DSS
= 55 V
I
D
= 37 A
g
s
R
DS(ON)
35 mΩ (V
GS
= 5 V)
R
DS(ON)
32 mΩ (V
GS
= 10 V)
GENERAL DESCRIPTION
N-channel enhancement mode, logic level, field-effect power transistor in a plastic envelope using ’trench’ technology.
The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching
applications.
The PHP37N06LT is supplied in the SOT78 (TO220AB) conventional leaded package.
The PHB37N06LT is supplied in the SOT404 surface mounting package.
The PHD37N06LT is supplied in the SOT428 surface mounting package.
PINNING
PIN
1
2
3
tab
DESCRIPTION
SOT78 (TO220AB)
tab
SOT404
tab
SOT428
tab
gate
drain
1
source
2
2
drain
1 23
1
3
1
3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
V
DSS
V
DGR
V
GS
I
D
I
DM
P
D
T
j
, T
stg
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Continuous drain current
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
CONDITIONS
T
j
= 25 ˚C to 175˚C
T
j
= 25 ˚C to 175˚C; R
GS
= 20 kΩ
T
mb
= 25 ˚C
T
mb
= 100 ˚C
T
mb
= 25 ˚C
T
mb
= 25 ˚C
MIN.
-
-
-
-
-
-
-
- 55
MAX.
55
55
±
13
37
26
148
100
175
UNIT
V
V
V
A
A
A
W
˚C
1
It is not possible to make connection to pin 2 of the SOT428 or SOT404 packages.
September 1998
1
Rev 1.400

PHB37N06LT/T3 Related Products

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Description TRANSISTOR 37 A, 55 V, 0.035 ohm, N-CHANNEL, Si, POWER, MOSFET, FET General Purpose Power TRANSISTOR 37 A, 55 V, 0.035 ohm, N-CHANNEL, Si, POWER, MOSFET, FET General Purpose Power TRANSISTOR 37 A, 55 V, 0.035 ohm, N-CHANNEL, Si, POWER, MOSFET, TO-220AB, FET General Purpose Power TRANSISTOR 37 A, 55 V, 0.035 ohm, N-CHANNEL, Si, POWER, MOSFET, FET General Purpose Power TRANSISTOR 37 A, 55 V, 0.035 ohm, N-CHANNEL, Si, POWER, MOSFET, FET General Purpose Power TRANSISTOR 37 A, 55 V, 0.035 ohm, N-CHANNEL, Si, POWER, MOSFET, FET General Purpose Power
Reach Compliance Code unknown unknown unknown unknown compliant unknow
ECCN code EAR99 EAR99 EAR99 EAR99 EAR99 EAR99
Avalanche Energy Efficiency Rating (Eas) 45 mJ 45 mJ 45 mJ 45 mJ 45 mJ 45 mJ
Shell connection DRAIN DRAIN DRAIN DRAIN DRAIN DRAIN
Configuration SINGLE WITH BUILT-IN DIODE SINGLE WITH BUILT-IN DIODE SINGLE WITH BUILT-IN DIODE SINGLE WITH BUILT-IN DIODE SINGLE WITH BUILT-IN DIODE SINGLE WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage 55 V 55 V 55 V 55 V 55 V 55 V
Maximum drain current (ID) 37 A 37 A 37 A 37 A 37 A 37 A
Maximum drain-source on-resistance 0.035 Ω 0.035 Ω 0.035 Ω 0.035 Ω 0.035 Ω 0.035 Ω
FET technology METAL-OXIDE SEMICONDUCTOR METAL-OXIDE SEMICONDUCTOR METAL-OXIDE SEMICONDUCTOR METAL-OXIDE SEMICONDUCTOR METAL-OXIDE SEMICONDUCTOR METAL-OXIDE SEMICONDUCTOR
JESD-30 code R-PSSO-G2 R-PSSO-G2 R-PSFM-T3 R-PSSO-G2 R-PSSO-G2 R-PSSO-G2
Number of components 1 1 1 1 1 1
Number of terminals 2 2 3 2 2 2
Operating mode ENHANCEMENT MODE ENHANCEMENT MODE ENHANCEMENT MODE ENHANCEMENT MODE ENHANCEMENT MODE ENHANCEMENT MODE
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE SMALL OUTLINE FLANGE MOUNT SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE
Polarity/channel type N-CHANNEL N-CHANNEL N-CHANNEL N-CHANNEL N-CHANNEL N-CHANNEL
Maximum pulsed drain current (IDM) 148 A 148 A 148 A 148 A 148 A 148 A
Certification status Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
surface mount YES YES NO YES YES YES
Terminal form GULL WING GULL WING THROUGH-HOLE GULL WING GULL WING GULL WING
Terminal location SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE
transistor applications SWITCHING SWITCHING SWITCHING SWITCHING SWITCHING SWITCHING
Transistor component materials SILICON SILICON SILICON SILICON SILICON SILICON
package instruction SMALL OUTLINE, R-PSSO-G2 SMALL OUTLINE, R-PSSO-G2 FLANGE MOUNT, R-PSFM-T3 SMALL OUTLINE, R-PSSO-G2 - -
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