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Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MC9S08FL16
Rev. 3, 11/2010
MC9S08FL16 Series
Covers: MC9S08FL16 and
MC9S08FL8
MC9S08FL16
32-Pin LQFP
873A-03
32-Pin SDIP
1376-02
Features:
8-Bit S08 Central Processor Unit (CPU)
• Up to 20 MHz CPU at 4.5 V to 5.5 V across
temperature range of –40 °C to 85 °C
• HC08 instruction set with added BGND instruction
• Support for up to 32 interrupt/reset sources
• Illegal address detection with reset
• Flash block protection
Development Support
• Single-wire background debug interface
• Breakpoint capability to allow single breakpoint
setting during in-circuit debugging (plus two more
breakpoints).
• On-chip in-circuit emulator (ICE) debug module
containing two comparators and nine trigger
modes.
On-Chip Memory
• Up to 16 KB flash read/program/erase over full
operating voltage and temperature
• Up to 1024-byte random-access memory (RAM)
• Security circuitry to prevent unauthorized access
to RAM and flash contents
Peripherals
• IPC
— Interrupt priority controller to provide
hardware based nested interrupt mechanism
•
ADC
— 12-channel, 8-bit resolution; 2.5
s
conversion time; automatic compare function;
1.7 mV/C temperature sensor; internal bandgap
reference channel; operation in stop; optional
hardware trigger; fully functional from 4.5 V to
5.5 V
•
TPM
— One 4-channel and one 2-channel
timer/pulse-width modulators (TPM) modules;
selectable input capture, output compare, or
buffered edge- or center-aligned PWM on each
channel
•
MTIM16
— One 16-bit modulo timer with optional
prescaler
• SCI
— One serial communications interface
module with optional 13-bit break; LIN extensions
Power-Saving Modes
• Two low power stop modes; reduced power wait
mode
• Allows clocks to remain enabled to specific
peripherals in stop3 mode
Clock Source Options
• Oscillator (XOSC) — Loop-control Pierce
oscillator; crystal or ceramic resonator range of
31.25 kHz to 39.0625 kHz or 1 MHz to 16 MHz
• Internal Clock Source (ICS) — Internal clock
source module containing a
frequency-locked-loop (FLL) controlled by internal
or external reference; precision trimming of
internal reference allows 0.2% resolution and 2%
deviation over temperature and voltage; supports
bus frequencies up to 10 MHz
Input/Output
• 30 GPIOs including 1 output-only pin and 1
input-only pin
System Protection
• Watchdog computer operating properly (COP)
reset with option to run from dedicated 1 kHz
internal clock source or bus clock
• Low-voltage detectionwith reset or interrupt;
selectable trip points
• Illegal opcode detection with reset
Package Options
• 32-pin SDIP
• 32-pin LQFP
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2009-2010. All rights reserved.
Table of Contents
1
2
3
4
5
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
System Clock Distribution . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . 9
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.2 Parameter Classification . . . . . . . . . . . . . . . . . . . 9
5.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 9
5.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . 10
5.5 ESD Protection and Latch-Up Immunity . . . . . . 11
5.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 12
5.7 Supply Current Characteristics . . . . . . . . . . . . . 17
5.8 External Oscillator (XOSC) and ICS
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .
5.9 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . .
5.9.1 Control Timing . . . . . . . . . . . . . . . . . . . . .
5.9.2 TPM Module Timing . . . . . . . . . . . . . . . .
5.10 ADC Characteristics . . . . . . . . . . . . . . . . . . . . .
5.11 Flash Specifications. . . . . . . . . . . . . . . . . . . . . .
5.12 EMC Performance . . . . . . . . . . . . . . . . . . . . . . .
5.12.1Radiated Emissions. . . . . . . . . . . . . . . . .
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . .
Package Information . . . . . . . . . . . . . . . . . . . . . . . . .
7.1 Mechanical Drawings. . . . . . . . . . . . . . . . . . . . .
19
21
22
23
24
26
27
27
27
28
28
6
7
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will
be the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://freescale.com/
The following revision history table summarizes changes contained in this document.
Rev
1
2
3
Date
March 18, 2009
July 20, 2009
Nov. 29, 2010
Initial public release.
Updated
Section 5.12, “EMC Performance.”
and corrected
Figure 1
and
Table 1.
Corrected default trim value to 31.25 kHz.
Updated
Table 7.
Description of Changes
Related Documentation
Find the most current versions of all documents at: http://www.freescale.com
Reference Manual
(MC9S08FL16RM)
Contains extensive product information including modes of operation, memory,
resets and interrupts, register definition, port pins, CPU, and all module
information.
MC9S08FL16 Series Data Sheet, Rev. 3
2
Freescale Semiconductor
MCU Block Diagram
1
MCU Block Diagram
The block diagram,
Figure 1,
shows the structure of MC9S08FL16 series MCU.
PTA0/ADP0
16-BIT MODULO TIMER
HCS08 CORE
(MTIM16)
TCLK
PTA1/ADP1
PTA2/ADP2
CPU
BDC
2-CH TIMER/PWM
MODULE (TPM2)
HCS08 SYSTEM CONTROL
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
COP
IRQ
LVD
INTERRUPT PRIORITY
CONTROLLER (IPC)
PTB0/RxD/ADP4
PTB1/TxD/ADP5
SERIAL COMMUNICATIONS
INTERFACE (SCI)
USER FLASH
MC9S08FL16 — 16,384 BYTES
MC9S08FL8 — 8,192 BYTES
4-CH TIMER/PWM
USER RAM
MC9S08FL16 — 1,024 BYTES
MC9S08FL8 — 768 BYTES
MODULE (TPM1)
TPM1CH[3:0]
TxD
RxD
PTB2/ADP6
TPM2CH[1:0]
PORT A
PTA3/ADP3
PTA4/BKGD/MS
PTA5/IRQ/TCLK/RESET
RESET
IRQ
PTA6/TPM2CH0
PTA7/TPM2CH1
ON-CHIP ICE AND
DEBUG MODUE (DBG)
PORT B
PTB3/ADP7
PTB4/TPM1CH0
PTB5/TPM1CH1
PTB6/XTAL
PTB7/EXTAL
20 MHz INTERNAL CLOCK
SOURCE (ICS)
EXTAL
XTAL
PTC0/ADP8
PTC1/ADP9
PTC2/ADP10
EXTERNAL OSCILLATOR
SOURCE (XOSC)
PORT C
PTC3/ADP11
PTC4
PTC5
V
DD
V
SS
VOLTAGE REGULATOR
PTC6
PTC7
12-CH 8-BIT
ANALOG-TO-DIGITAL
CONVERTER (ADC)
ADP[11:0]
PTD0
PTD1
V
REFH
V
REFL
V
DDA
V
SSA
PORT D
PTD2/TPM1CH2
PTD3/TPM1CH3
PTD4
PTD5
NOTE
1. PTA4 is output only when used as port pin.
2. PTA5 is input only when used as port pin.
Figure 1. MC9S08FL16 Series Block Diagram
MC9S08FL16 Series Data Sheet, Rev. 3
Freescale Semiconductor
3
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