D ts e t
aa h e
R c e t r lc r nc
o h se Ee to is
Ma u a t r dCo o e t
n fc u e
mp n n s
R c e tr b a d d c mp n ns ae
o h se rn e
o oet r
ma ua trd u ig ete dewaes
n fcue sn i r i/ fr
h
p rh s d f m te oiia s p l r
uc a e r
o h r n l u pi s
g
e
o R c e tr waes rce td f m
r o h se
fr e rae r
o
te oiia I. Al rce t n ae
h
r nl P
g
l e rai s r
o
d n wi tea p o a o teOC
o e t h p rv l f h
h
M.
P r aetse u igoiia fcoy
at r e td sn r n la tr
s
g
ts p o rmso R c e tr e eo e
e t rga
r o h se d v lp d
ts s lt n t g aa te p o u t
e t oui s o u rne
o
rd c
me t o e c e teOC d t s e t
es r x e d h
M aa h e.
Qu l yOv riw
ai
t
e ve
• IO- 0 1
S 90
•A 92 cr ct n
S 1 0 et ai
i
o
• Qu l e Ma ua trr Ls (
ai d
n fcues it QML MI- R -
) LP F
385
53
•C a sQ Mitr
ls
lay
i
•C a sVS a eL v l
ls
p c ee
• Qu l e S p l r Ls o D sr uos( L )
ai d u pi s it f it b tr QS D
e
i
•R c e trsacic l u pir oD A a d
o h se i
r ia s p l t L n
t
e
me t aln u t a dD A sa d r s
es lid sr n L tn ad .
y
R c e tr lcrnc , L i c mmi e t
o h se Ee t is L C s o
o
tdo
t
s p ligp o u t ta s t f c so r x e t-
u pyn rd cs h t ai y u tme e p ca
s
t n fr u lya daee u loto eoiial
i s o q ai n r q a t h s r n l
o
t
g
y
s p l db id sr ma ua trr.
u pi
e yn ut
y n fcues
T eoiia ma ua trr d ts e t c o a yn ti d c me t e e t tep r r n e
h r n l n fcue’ aa h e a c mp n ig hs o u n r cs h ef ma c
g
s
o
a ds e ic t n o teR c e tr n fcue v rino ti d vc . o h se Ee t n
n p c ai s f h o h se ma ua trd eso f hs e ie R c e tr lcr -
o
o
isg aa te tep r r n eo i s mio d co p o u t t teoiia OE s e ic -
c u rne s h ef ma c ft e c n u tr rd cs o h r n l M p c a
o
s
g
t n .T pc lv le aefr eee c p r o e o l. eti mii m o ma i m rt g
i s ‘y ia’ au s r o rfrn e up s s ny C r n nmu
o
a
r xmu ai s
n
ma b b s do p o u t h rceiain d sg , i lt n o s mpetsig
y e a e n rd c c aa tr t , e in smuai , r a l e t .
z o
o
n
© 2 1 R cetr l t n s LC Al i t R sre 0 1 2 1
0 3 ohs E cr i , L . lRg s eevd 7 1 0 3
e e oc
h
T l r m r, l s v iw wrcl . m
o e n oe p ae it w . e c o
a
e
s
o ec
Freescale Semiconductor
Technical Data
Document Number: MC33810
Rev. 10.0, 4/2011
Automotive Engine Control IC
The 33810 is an eight channel output driver IC intended for
automotive engine control applications. The IC consists of four
integrated low side drivers and four low side gate pre-drivers. The low
side drivers are suitable for driving fuel injectors, solenoids, lamps,
and relays. The four gate pre-drivers can function either as ignition
IGBT gate pre-drivers or as general purpose MOSFET gate pre-
drivers.
When configured as ignition IGBT gate pre-drivers, additional
features are enabled such as spark duration, dwell time, and ignition
coil current sense. When configured as a general purpose gate pre-
driver, the 33810 provides external MOSFETs with short circuit
protection, inductive flyback protection and diagnostics. The device is
packaged in a 32 pin (0.65mm pitch) exposed pad SOIC.
Features
• Designed to operate over the range of 4.5V
≤
VPWR
≤
36V
• Quad ignition IGBT or MOSFET gate pre-driver with Parallel/SPI
and/or PWM control
• Quad injector driver with Parallel/SPI control
• Interfaces directly to MCU using 3.3V / 5.0V SPI protocol
• Injector driver current limit - 4.5A max.
• Independent fault protection and diagnostics
• VPWR standby current 10μA max.
• Pb-free packaging designated by suffix code EK
VBAT
33810
ENGINE CONTROL
EK SUFFIX (Pb-FREE)
98ASA10556D
32 PIN SOICW EP
ORDERING INFORMATION
Device
MCZ33810EK/R2
Temperature
Range (T
A
)
-40°C to 125°C
Package
32 SOICW-EP
33810
V
DD
VPWR
VDD
OUT0
OUT1
OUT2
OUT3
GND
FB0
GD0
FB1
GD1
FB2
GD2
FB3
GD3
RSP
RSN
V
BAT
V
BAT
V
BAT
V
BAT
V
BAT
MCU
MOSI
SCLK
CS
MISO
ETPU
ETPU
ETPU
ETPU
GPIO
ETPU
ETPU
ETPU
SI
SCLK
CS
SO
DIN0
DIN3
GIN0
GIN3
OUT EN
SPKDUR
NOMI
MAXI
V
BAT
V
BAT
V
BAT
Figure 1. MC33810 Simplified Application Diagram
Freescale Semiconductor, Inc. reserves the right to change the detail specifications,
as may be required, to permit improvements in the design of its products.
© Freescale Semiconductor, Inc., 2006 - 2011. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VPWR
VDD
V
DD
~50 µA
V
DD
~50 µA
LOGIC CONTROL
VPWR, VDD
V8.0 Analog
V2.5 Logic
POR, Over-voltage
Under-voltage
Oscillator
Bandgap
Bias
V2.5
Outputs 0 to 3
CS
SI
SCLK
OUTEN
~15 µA
V
DD
~15 µA
SPI
INTERFACE
SO
DIN0
~50 µA
PARALLEL
CONTROL
Gate Control
Current Limit
Temperature Limit
Short/Open
+
–
lLimit
VOC1
OUT0
OUT1
OUT2
OUT3
75 µA
DIN1
~50 µA
R
S
DIN2
~50 µA
PWM
CONTROLLER
Exposed
Pad
+
–
DIN3
~50 µA
NOMI,MAXI
DAC
SPARK DURATION
Open Secondary
SPARK
DAC
~50 µA
SPI
SPI
100 µA
VLVC
+
–
GIN0
~50 µA
+
V
PWR
−
FB0
FB1
FB2
FB3
GPGD
Only
GIN1
VOC
GIN2
~50 µA
GATE DRIVE
CONTROL
Low V
Clamp
GPGD
Clamp
GIN3
~50 µA
VDD
~5 0µA
NOMI
+
–
GD0
GD1
GD2
GD3
DAC
SPKDUR
MAXI
+
–
RSP
DAC
RSN
NOMI
MAXI
Exposed Pad
GND
Figure 2. 33810 Simplified Internal Block Diagram
33810
2
Analog Integrated Circuit Device Data
Freescale Semiconductor
PIN CONNECTIONS
PIN CONNECTIONS
OUT0
FB0
GD0
CS
SCLK
SI
SO
VDD
OUTEN
DIN0
DIN1
DIN2
DIN3
GD1
FB1
OUT1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OUT2
FB2
GD2
MAXI
NOMI
RSN
RSP
VPWR
GIN0
GIN1
GIN2
GIN3
SPKDUR
GD3
FB3
OUT3
GND
Figure 3. 33810 Pin Connections
Table 1. 33810 Pin Definitions
A functional description of each pin can be found in the Functional Pin Description section beginning on
page 15.
Pin Number
8
Pin Name
VDD
Pin Function
Input
Formal Name
Digital Logic Supply
Voltage
Definition
The VDD input supply voltage determines the interface voltage levels
between the device and the MCU, and is used to supply power to the
Serial Out buffer (SO), SPKDUR buffer, MAXI, NOMI, and pull-up current
source for the Chip Select (CS).
The SI input pin is used to receive serial data from the MCU.
The SCLK input pin is used to clock in and out the serial data on the SI
and SO pins, while being addressed by the CS.
The Chip Select input pin is an active low signal sent by the MCU to
indicate that the device is being addressed. This input requires CMOS
logic levels and has an internal active pull-up current source.
The SO output pin is used to transmit serial data from the device to the
MCU.
Active HIGH input control for injector outputs OUT0 - 3. The parallel input
data is logically OR’d with the corresponding SPI input data register
contents.
These pins are the active HIGH input control for IGBT/General Purpose
Gate Driver outputs 0 - 3. The parallel input data is logically OR'd with the
corresponding SPI input data register contents in General Purpose Mode
Only.
6
5
4
SI
SCLK
CS
Input
Input
Input
Serial Input Data
Serial Clock Input
Chip Select
7
SO
Output
Input
Serial Output Data
Driver Input 0, Driver
Input 1, Driver Input 2,
Driver Input 3
Gate Driver Input 0
Gate Driver Input 1
Gate Driver Input 2
Gate Driver Input 3
10, 11, 12, 13 DIN0,DIN1,
DIN2,DIN3
24, 23, 22, 21 GIN0,GIN1,
GIN2,GIN3
Input
20
SPKDUR
Output
Spark Duration Output This pin is the Spark Duration Output. This open drain output is low while
feedback inputs FB0 through FB3 are above the programmed spark
detection threshold.
Analog Supply Voltage VPWR is the main voltage input for all internal analog bias circuitry.
Ground
The exposed pad is the only ground reference for analog, digital and
power ground connections. As such, it must be soldered directly to a low
impedance ground plane for both electrical and thermal considerations.
For more information about this package, please see application note
AN2409 on the Freescale Web site,
www.freescale.com
25
Exposed Pad
(bottom of
package)
VPWR
GND
Input
Ground
33810
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
PIN CONNECTIONS
Table 1. 33810 Pin Definitions (continued)
A functional description of each pin can be found in the Functional Pin Description section beginning on
page 15.
Pin Number
9
Pin Name
OUTEN
Pin Function
Input
Formal Name
Output Enable
Definition
The Output Enable pin (OUTEN) is an active low input. When the OUTEN
pin is low, the device outputs are active. The outputs are disabled when
OUTEN is high.
This pin is the Maximum Ignition Coil Current output flag. This output is
asserted when the IGBT Collector-Emitter current exceeds the selected
level of the DAC. This signal also latches off the gate pre-drive outputs
when configured as a General Purpose Gate pre-Driver. The MAXI
current level is determined by the voltage drop across an external sense
resistor connected to pins RSP and RSN.
This pin is the Nominal Ignition Coil Current output flag. This output is
asserted when the IGBT Collector-Emitter current exceeds the level
selected by the DAC.
In IGBT ignition gate pre-driver mode, these feedback inputs monitor the
IGBT's collector voltage to provide the spark duration timer control signal.
IGBT/General Purpose Gate pre-driver outputs are controlled by GIN0 -
GIN3. Pull-up and pull-down current sources are used to provide a
controlled slew rate to an external IGBT or MOSFET connected as a low
side driver.
This pin is the Positive input of a current sense amplifier.
This pin is the Negative input of a current sense amplifier.
These pin are the Open drain low side injector driver outputs.
29
MAXI
Output
Maximum Ignition Coil
Current
28
NOMI
Output
Nominal Ignition Coil
Current
Feedback Voltage
Sense
Gate Drive Output
2, 15, 31, 18
3, 14, 30,19
FB0 - FB3
GD0 -GD3
Input
Output
26
27
RSP
RSN
Input
Input
Output
Resistor Sense
Positive
Resistor Sense
Negative
Low Side Injector
Driver Output
1, 16, 32, 17 OUT0 -OUT3
33810
4
Analog Integrated Circuit Device Data
Freescale Semiconductor
京公网安备 11010802033920号
EEWORLD
