Small Signal Transistor
PROCESS
CP707
PNP - Darlington Transistor Chip
PROCESS DETAILS
Process
Die Size
Die Thickness
Base Bonding Pad Area
Emitter Bonding Pad Area
Top Side Metalization
Back Side Metalization
GEOMETRY
GROSS DIE PER 4 INCH WAFER
15,440
PRINCIPAL DEVICE TYPES
CMPTA63
CMPTA64
CXTA64
CZTA64
MPSA63
MPSA64
EPITAXIAL PLANAR
27 x 27 MILS
9.0 MILS
5.3 x 3.8 MILS
5.3 x 6.5 MILS
Al - 30,000Å
Au - 18,000Å
BACKSIDE COLLECTOR
145 Adams Avenue
Hauppauge, NY 11788 USA
Tel: (631) 435-1110
Fax: (631) 435-1824
www.centralsemi.com
R4 (23-August 2006)