HIP2120, HIP2121
SIGNS
NOT RECOMMENDED FOR NEW DE
T
NO RECOMMENDED REPLACEMEN
nter at
contact our Technical Support Ce
m/tsc
1-888-INTERSIL or www.intersil.co
DATASHEET
FN7668
Rev 0.00
December 23, 2011
100V, 2A Peak, High Frequency Half-Bridge Drivers with Adjustable Dead Time
Control and PWM Input
The HIP2120 and HIP2121 are 100V, high frequency, half-bridge
MOSFET driver ICs. They are based on the popular ISL2100A and
ISL2101A half-bridge drivers.
These drivers have a programmable dead-time to insure
break-before-make operation between the high-side and low-side
drivers. The dead-time is adjustable up to 250ns.
A single PWM logic input controls both bridge outputs (HO, LO). An
enable pin (EN), when low, drives both outputs to a low state. All
logic inputs are V
DD
tolerant and the HIP2120 has CMOS inputs
with hysteresis for superior operation in noisy environments.
The HIP2120 has hysteretic inputs with thresholds that are
proportional to V
DD
. The HIP2121 has 3.3V logic/TTL compatible
inputs.
Two package options are provided. The 10 Ld 4x4 DFN package
has standard pinouts. The 9 Ld 4x4 DFN package omits pin 2 to
comply with 100V conductor spacing per IPC-2221.
Features
• 9 Ld TDFN “B” Package Compliant with 100V Conductor
Spacing Guidelines per IPC-2221
• Break-Before-Make Dead-Time Prevents Shoot-through and
is adjustable up to 220ns
• Bootstrap Supply Max Voltage to 114VDC
• Wide Supply Voltage Range (8V to 14V)
• Supply Undervoltage Protection
• CMOS Compatible Input Thresholds with Hysteresis
(HIP2120)
• 1.6/1 Typical Output Pull-up/Pull-down Resistance
• On-Chip 1 Bootstrap Diode
Applications
• Telecom Half-Bridge DC/DC Converters
• UPS and Inverters
• Motor Drives
• Class-D Amplifiers
• Forward Converter with Active Clamp
Related Literature
•
FN7670
“HIP2122, HIP2123 100V, 2A Peak, High
Frequency Half-Bridge Driver with Delay Timers”
100V max
HALF BRIDGE
VDD
PWM
PWM
CONTROLLER
EN
HIP2120/21
HB
HO
HS
RDT
VSS
EPAD
LO
FEEDBACK
WITH
ISOLATION
SECONDARY
CIRCUITS
DEAD-TIME (ns)
200
160
140
120
100
80
60
40
20
8
16
24
32
40
48 56 64
80
R
DT
(k)
FIGURE 1. TYPICAL APPLICATION
FIGURE 2. DEAD-TIME vs TIMING RESISTOR
FN7668 Rev 0.00
December 23, 2011
Page 1 of 16
HIP2120, HIP2121
Block Diagram
VDD
HB
HIP2120,
HIP2121
HIP2121
PWM
HIP2120/21
UNDER
VOLTAGE
LEVEL
SHIFT
HO
HS
DELAY
RDT
Optional
inversion
for future
part
numbers
UNDER
VOLTAGE
DELAY
LO
EN
VSS
EPAD IS
ELECTRICALLY
ISOLATED
EPAD
HIP2121
HIP2120/21
Pin Configurations
HIP2120, HIP2121
(10 LD 4X4 TDFN)
TOP VIEW
VDD
HB
HO
HS
NC
1
2
3
4
5
EPAD
10
LO
9
8
7
6
VSS
PWM
EN
RDT
HB
HO
HS
3
4
5
EPAD
VDD
1
HIP2120, HIP2121
(9 LD 4X4 TDFN)
TOP VIEW
10
LO
9
8
7
6
VSS
PWM
EN
RDT
FN7668 Rev 0.00
December 23, 2011
Page 2 of 16
HIP2120, HIP2121
Pin Descriptions
10 LD
1
2
3
4
8
7
9
10
5
6
-
9 LD
1
3
4
5
8
7
9
10
-
6
-
SYMBOL
VDD
HB
HO
HS
PWM
EN
VSS
LO
NC
RDT
EPAD
DESCRIPTION
Positive supply voltage for lower gate driver. Decouple this pin with a ceramic capacitor to
VSS.
High-side bootstrap supply voltage referenced to HS. Connect the positive side of the
bootstrap capacitor to this pin. Bootstrap diode is on-chip.
High-side output. Connect to gate of high-side power MOSFET.
High-side source connection. Connect to source of high-side power MOSFET. Connect
negative side of bootstrap capacitor to this pin.
PWM input. For PWM = 1, HO = 1 and LO = 0. For PWM = 0, HO = 0 and LO = 1.
Output enable, when low, HO = LO = 0
Negative voltage supply, which will generally be ground.
Low-side output. Connect to gate of low-side power MOSFET.
No Connect. This pin is isolated from all other pins.
A resistor connected between this pin and VSS adds additional delay time to the falling and
rising edges of the PWM input.
Exposed pad. Connect to ground or float. The EPAD is electrically isolated from all other
pins.
Ordering Information
PART NUMBER
(Notes 1, 2, 4)
HIP2120FRTAZ
HIP2121FRTAZ
HIP2120FRTBZ (Note 3)
HIP2121FRTBZ (Note 3)
NOTES:
1. Please refer to
TB347
for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. “B” package option has alternate pin assignments for compliance with 100V Conductor Spacing Guidelines per IPC-2221. Note that Pin 2 is omitted
for additional spacing.
4. For Moisture Sensitivity Level (MSL), please see device information page for
HIP2120, HIP2121.
For more information on MSL please see tech brief
TB363.
PART
MARKING
HIP 2120AZ
HIP 2121AZ
HIP 2120BZ
HIP 2121BZ
INPUT
CMOS
3.3V/TTL
CMOS
3.3V/TTL
TEMP. RANGE
(°C)
-40 +125
-40 +125
-40 +125
-40 +125
PACKAGE
(Pb-Free)
10 Ld 4x4 TDFN
10 Ld 4x4 TDFN
9 Ld 4x4 TDFN
9 Ld 4x4 TDFN
PKG.
DWG. #
L10.4x4
L10.4x4
L9.4x4
L9.4x4
FN7668 Rev 0.00
December 23, 2011
Page 3 of 16
HIP2120, HIP2121
Table of Contents
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Maximum Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Typical Performance Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Selecting the Boot Capacitor Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Typical Application Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Transients on HS Node . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
PC Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
EPAD Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
L9.4x4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
L10.4x4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
FN7668 Rev 0.00
December 23, 2011
Page 4 of 16
HIP2120, HIP2121
Absolute Maximum Ratings
Supply Voltage, V
DD
, V
HB
- V
HS
(Notes 5, 6) . . . . . . . . . . . . . . . -0.3V to 18V
PWM and EN Input Voltage (Note 6) . . . . . . . . . . . . . . .-0.3V to VDD + 0.3V
Voltage on LO (Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to VDD + 0.3V
Voltage on HO (Note 6) . . . . . . . . . . . . . . . . . . . . . VHS - 0.3V to VHB + 0.3V
Voltage on HS (Continuous) (Note 6) . . . . . . . . . . . . . . . . . . . . . -1V to 110V
Voltage on HB (Note 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118V
Average Current in V
DD
to HB Diode . . . . . . . . . . . . . . . . . . . . . . . . . 100mA
Thermal Information
Thermal Resistance (Typical)
JA
(°C/W)
JC
(°C/W)
10 Ld TDFN (Notes 7, 8) . . . . . . . . . . . . . . .
42
4
9 Ld TDFN (Notes 7, 8) . . . . . . . . . . . . . . . .
42
4
Max Power Dissipation at +25°C in Free Air
10 Ld TDFN (Notes 7, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0W
9 Ld TDFN (Notes 7, 8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1W
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Maximum Recommended Operating
Conditions
Supply Voltage, V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V to 14V
Voltage on HS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to 100V
Voltage on HS . . . . . . . . . . . . . . . . . . . . . .(Repetitive Transient) -5V to 105V
Voltage on HB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
HS
+ 8V to V
HS
+ 14V and
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DD
- 1V to V
DD
+ 100V
HS Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <50V/ns
ESD Ratings
Human Body Model Class 2 (Tested per JESD22-A114E). . . . . . . . . . 3000V
Machine Model Class B (Tested per JESD22-A115-A). . . . . . . . . . . . . . 300V
Charged Device Model Class IV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
5. The HIP2120 and HIP2121 are capable of derated operation at supply voltages exceeding 14V. Figure 20 shows the high-side voltage derating curve
for this mode of operation.
6. All voltages referenced to V
SS
unless otherwise specified.
7.
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief
TB379.
8. For
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
V
DD
= V
HB
= 12V, V
SS
= V
HS
= 0V, R
DT
= 0
K
, PWM = 0V, No Load on LO or HO, Unless Otherwise Specified.
Boldface limits apply over the operating temperature range, -40°C to +125°C.
T
A
= +25°C
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
T
A
= -40°C to +125°C
MIN (Note 9) MAX (Note 9)
UNITS
SUPPLY CURRENTS
V
DD
Quiescent Current
I
DD80
I
DD8k
I
DDO80k
I
DDO8k
I
HB
I
HBO
I
HBS
I
HBSO
R
DT
= 80k
R
DT
= 8k
f = 500kHz, R
DT
= 80k
f = 500kHz, R
DT
= 8k
LI = HI = 0V
f = 500kHz
LI = HI = 0V; V
HB
= V
HS
= 114V
f = 500kHz; V
HB
= V
HS
= 114V
-
-
-
-
-
-
-
-
470
1.0
2.5
3.4
65
2.0
0.05
1.2
850
2.1
3
4
115
2.5
1.5
1.5
-
-
-
-
-
-
-
-
900
2.2
3
4
150
3
10
1.6
µA
mA
mA
mA
µA
mA
µA
mA
V
DD
Operating Current
Total HB Quiescent Current
Total HB Operating Current
HB to V
SS
Current, Quiescent
HB to V
SS
Current, Operating
INPUT PINS
Low Level Input Voltage
Threshold
Low Level Input Voltage
Threshold
High Level Input Voltage
Threshold
High Level Input Voltage
Threshold
V
IL
V
IL
V
IH
V
IH
HIP2120 (CMOS)
HIP2121 (3.3V/TTL)
HIP2120 (CMOS)
HIP2121 ((3.3V/TTL)
3.7
1.4
-
-
4.4
1.8
6.54
1.8
-
-
7.93
2.2
2.7
1.2
5.3
-
-
-
8.2
2.4
V
V
V
V
FN7668 Rev 0.00
December 23, 2011
Page 5 of 16
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