SiC779
Vishay Siliconix
Integrated DrMOS Power Stage
DESCRIPTION
The SiC779 is an integrated solution that contains PWM
optimized n-channel MOSFETs (high side and low side) and
a full featured MOSFET driver IC. The device complies with
the Intel DrMOS standard for desktop and server V
core
power
stages. The SiC779 delivers up to 40 A continuous output
current and operates from an input voltage range of 3 V to
16 V. The integrated MOSFETs are optimized for output
voltages in the ranges of 0.8 V to 2.0 V with a nominal input
voltage of 12 V. The device can also deliver very high power
at 5 V output for ASIC applications.
The SiC779 incorporates an advanced MOSFET gate driver
IC. This IC accepts a single PWM input from the V
R
controller
and converts it into the high side and low side MOSFET gate
drive signals. The driver IC is designed to implement the skip
mode (SMOD) function for light load efficiency improvement.
Adaptive dead time control also works to improve efficiency
at all load points. The SiC779 has a thermal warning (THDN)
that alerts the system of excessive junction temperature. The
driver IC includes an enable pin, UVLO and shoot through
protection.
The SiC779 is optimized for high frequency buck
applications. Operating frequencies in excess of 1 MHz can
easily be achieved.
The SiC779 is packaged in Vishay Siliconix high
performance PowerPAK MLP 6 x 6 package. Compact
co-packaging of components helps to reduce stray
inductance, and hence increases efficiency.
FEATURES
• Industry benchmark Gen III MOSFETs with
integrated Schottky diode
• DrMOS compliant gate driver IC
• Enables V
core
switching at 1 MHz
• Easily achieve > 93 % efficiency in multi-phase,
low output voltage solutions
• Low ringing on the VSWH pin reduces EMI
• Pin compatible with DrMOS 6 x 6 version 4.0
• Tri-state PWM input function prevents negative output
voltage swing
• 5 V logic levels on PWM
• MOSFET threshold voltage optimized for 5 V driver bias
supply
• Automatic skip mode operation (SMOD) for light load
efficiency
• Under-voltage lockout
• Built-in bootstrap schottky diode
• Adaptive deadtime and shoot through protection
• Thermal shutdown warning flag
• Low profile, thermally enhanced PowerPAK
®
MLP 6 x 6
40 pin package
• Halogen-free according to IEC 61249-2-21 definition
•
Compliant to RoHS Directive 2002/95/EC
APPLICATIONS
• CPU and GPU core voltage regulation
• Server, computer, workstation, game console, graphics
boards, PC
SiC779 APPLICATION DIAGRAM
5
V
V
DRV
GH
V
IN
V
IN
V
CIN
SMOD
Gate Driver
DSBL#
PWM
PWM
THDN
Controller
BOOT
V
SWH
PHASE
V
O
SiC779CD
P
GND
C
GND
Figure 1
Document Number: 67538
S11-0703-Rev. B, 18-Apr-11
www.vishay.com
1
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
GL
SiC779
Vishay Siliconix
ORDERING INFORMATION
Part Number
SiC779CD-T1-GE3
SiC779DB
Package
PowerPAK MLP66-40
Reference board
ABSOLUTE MAXIMUM RATINGS
(T
A
= 25 °C, unless otherwise noted)
Parameter
Input Voltage
Switch Node Voltage (DC)
Drive Input Voltage
Control Input Voltage
Logic Pins
Boot Voltage DC (referenced to C
GND
)
Boot Voltage < 200 ns Transient (referenced to C
GND
)
Boot to Phase Voltage DC
Boot to Phase Voltage < 200 ns
Ambient Temperature Range
Maximum Junction Temperature
Storage Junction Temperature
Symbol
V
IN
V
SW
V
DRV
V
CIN
V
PWM
, V
DSBL#
,
V
THDN
, V
SMOD
V
BS
V
BS_PH
T
A
T
J
T
STG
- 65
Min.
- 0.3
- 0.3
- 0.3
- 0.3
- 0.3
- 0.3
- 0.3
- 0.3
- 0.3
- 40
Max.
20
20
7
7
V
CIN
+ 0.3
27
29
7
9
125
150
150
260
°C
V
Unit
Soldering Peak Temperature
Note:
a. T
A
= 25 °C and all voltages referenced to P
GND
= C
GND
unless otherwise noted.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to absolute maximum rating/conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Parameter
Input Voltage
Control Input Voltage
Drive Input Voltage
Switch Node
Symbol
V
IN
V
CIN
V
DRV
V
SW_DC
Min.
3
4.5
4.5
12
Typ.
12
Max.
16
5.5
5.5
16
V
Unit
Note:
a. Recommended operating conditions are specified over the entire temperature range, and all voltages referenced to P
GND
= C
GND
unless
otherwise noted.
THERMAL RESISTANCE RATINGS
Parameter
Maximum Power Dissipation at T
PCB
= 25 °C
Maximum Power Dissipation at T
PCB
= 100 °C
Thermal Resistance from Junction to Top
Thermal Resistance from Junction to PCB
Symbol
P
D_25C
P
D_100C
R
th_J_TOP
R
th_J_PCB
Typ.
Max.
25
10
15
5
Unit
W
°C/W
www.vishay.com
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Document Number: 67538
S11-0703-Rev. B, 18-Apr-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
SiC779
Vishay Siliconix
ELECTRICAL SPECIFICATIONS
Test Conditions Unless Specified
V
DSBL#
= V
SMOD
= 5 V,
V
IN
= 12 V, V
VDRV
= V
VCIN
5 V,
T
A
= 25 °C
V
DSBL#
= 0 V, no switching
V
CIN
Control Input Current
I
VCIN
V
DSBL#
= 5 V, no switching
V
DSBL#
= 5 V, f
s
= 300 kHz, D = 0.1
Drive Input Current (Dynamic)
Bootstrap Supply
Bootstrap Switch Forward Voltage
Control Inputs (PWM, DSBL#, SMOD)
PWM Rising Threshold
PWM Falling Threshold
PWM Tristate Rising Threshold
PWM Tristate Falling Threshold
PWM Tristate Rising Threshold Hysteresis
PWM Tristate Falling Threshold Hysteresis
Tristate Hold-Off Time
b
PWM Input Current
SMOD, DSBL# Logic Input Voltage
Pull Down Impedance
THDN Output Low
Protection
Thermal Warning Flag Set
Thermal Warning Flag Clear
Thermal Warning Flag Hysteresis
Under Voltage Lockout
Under Voltage Lockout
Under Voltage Lockout Hysteresis
High Side Gate Discharge Resistor
b
Parameter
Power Supplies
Symbol
Min.
Typ.
a
60
400
600
15
48
0.60
Max.
Unit
µA
22
70
0.75
4.2
1.2
1.8
4.0
mV
ns
µA
V
V
V
I
VDRV
f
s
= 300 kHz, D = 0.1
f
s
= 1000 kHz, D = 0.1
V
VCIN
= 5 V, forward bias current 2 mA
3.5
0.8
0.9
3.4
mA
V
BS Diode
V
th_pwm_r
V
th_pwm_f
V
th_tri_r
V
th_tri_f
V
hys_tri_r
V
hys_tri_f
t
TSHO
I
PWM
V
LOGIC_LH
V
LOGIC_LH
R
THDN
V
THDNL
V
3.8
1.0
1.3
3.7
300
170
150
V
PWM
= 5 V
V
PWM
= 0 V
Rising (low to high)
Falling (high to low)
5 k resistor pull-up to V
CIN
2
250
- 250
0.8
40
0.07
150
135
15
°C
3.9
V
UVLO
V
UVLO_HYST
R
HS_DSCRG
Rising, on threshold
Falling, off threshold
V
VDRV
= V
VCIN
= 0 V; V
IN
= 12 V
2.5
3.3
2.9
400
20.2
V
mV
k
Notes:
a. Typical limits are established by characterization and are not production tested.
b. Guaranteed by design.
TIMING SPECIFICATIONS
Test Conditions Unless Specified
V
VDRV
= V
VCIN
= V
DSBL#
= 5 V,
V
VIN
= 12 V, T
A
= 25 °C
25 % of PWM to 90 % of GH
10 % to 90 % of GH
90 % to 10 % of GH
75 % of PWM to 90 % of GL
10 % to 90 % of GL
90 % to 10 % of GL
10 % of GL to 10 % of GH
10 % of GH to 10 % of GL
10
Parameter
Turn Off Propagation Delay
High Side
a
Rise Time High Side
Fall Time High Side
Turn Off Propagation Delay
Low Side
a
Rise Time Low Side
Fall Time Low Side
Dead Time Rising
Dead Time Falling
Symbol
t
d_on_HS
t
r_HS
t
f_HS
t
d_off_LS
t
r_LS
t
f_LS
t
dead_on
t
dead_off
Min.
10
Typ.
20
8
8
20
15
8
15
15
Max.
30
Unit
30
ns
Note:
a. Min. and Max. are not 100 % production tested.
Document Number: 67538
S11-0703-Rev. B, 18-Apr-11
www.vishay.com
3
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
SiC779
Vishay Siliconix
DETAILED OPERATIONAL DESCRIPTION
PWM Input with Tristate Function
The PWM input receives the PWM control signal from the V
R
controller IC. The PWM input is designed to be compatible
with standard controllers using two state logic (H and L) and
advanced controllers that incorporate Tristate logic (H, L and
Tristate) on the PWM output. For two state logic, the PWM
input operates as follows. When PWM is driven above
V
th_pwm_r
the low side is turned off and the high side is turned
on. When PWM input is driven below V
th_pwm_f
the high side
turns off and the Low side turns on. For Tristate logic, the
PWM input operates as above for driving the MOSFETs.
However, there is an third state that is entered into as the
PWM output of Tristate compatible controller enters its high
impedance state during shut-down. The high impedance
state of the controller's PWM output allows the SiC779 to pull
the PWM input into the Tristate region (see the Tristate
Voltage Threshold Diagram below). If the PWM input stays in
this region for the Tristate Hold-Off Period, t
TSHO
, both high
side and low side MOSFETs are turned off. This function
allows the V
R
phase to be disabled without negative output
voltage swing caused by inductor ringing and saves a
Schottky diode clamp. The PWM and Tristate regions are
separated by hysteresis to prevent false triggering. The
SiC779 incorporates PWM voltage thresholds that are
compatible with 5 V logic.
Disable (DSBL#)
In the low state, the DSBL# pin shuts down the driver IC and
disables both high-side and low-side MOSFET. In this state,
the standby current is minimized. If DSBL# is left
unconnected an internal pull-down resistor will pull the pin
down to C
GND
and shut down the IC.
Diode Emulation Mode (SMOD) Skip Mode
When SMOD pin is low the diode emulation mode is enabled.
This is a non-synchronous conversion mode that improves
light load efficiency by reducing switching losses. Conducted
losses that occur in synchronous buck regulators when
inductor current is negative are also reduced. Circuitry in the
gate drive IC detects the inductor valley current when
inductor current crosses zero and automatically stops
switching the low side MOSFET. See SMOD Operation
Diagram for additional details. This function can be also be
used for a pre-biased output voltage. If SMOD is left
unconnected, an internal pull up resistor will pull the pin up to
V
CIN
(Logic High) to disable the SMOD function.
Thermal Shutdown Warning (THDN)
The THDN pin is an open drain signal that flags the presence
of excessive junction temperature. Connect a maximum of
20 k to pull this pin up to V
CIN
. An internal temperature
sensor detects the junction temperature. The temperature
threshold is 150 °C. When this junction temperature is
exceeded the THDN flag is set. When the junction
temperature drops below 135 °C the device will clear the
THDN signal. The SiC779 does not stop operation when the
flag is set. The decision to shutdown must be made by an
external thermal control function.
Voltage Input (V
IN
)
This is the power input to the drain of the high-side Power
MOSFET. This pin is connected to the high power
intermediate BUS rail.
Switch Node (V
SWH
and PHASE)
The Switch node V
SWH
is the circuit PWM regulated output.
This is the output applied to the filter circuit to deliver the
regulated high output for the buck converter. The PHASE pin
is internally connected to the switch node V
SWH
. This pin is
to be used exclusively as the return pin for the BOOT
capacitor. A 20.2 k resistor is connected between GH and
PHASE to provide a discharge path for the HS MOSFET in
the event that V
CIN
goes to zero while V
IN
is still applied.
Ground connections (C
GND
and P
GND
)
P
GND
(power ground) should be externally connected to
C
GND
(control signal ground). The layout of the Printed
Circuit Board should be such that the inductance separating
the C
GND
and P
GND
should be a minimum. Transient
differences due to inductance effects between these two pins
should not exceed 0.5 V.
Control and Drive Supply Voltage Input (V
DRV
,V
CIN
)
V
CIN
is the bias supply for the gate drive control IC. V
DRV
is
the bias supply for the gate drivers. It is recommended to
separate these pins through a resistor. This creates a low
pass filtering effect to avoid coupling of high frequency gate
drive noise into the IC.
Bootstrap Circuit (BOOT)
The internal bootstrap switch and an external bootstrap
capacitor form a charge pump that supplies voltage to the
BOOT pin. An integrated bootstrap diode is incorporated so
that only an external capacitor is necessary to complete the
bootstrap circuit. Connect a boot strap capacitor with one leg
tied to BOOT pin and the other tied to PHASE pin.
Shoot-Through Protection and Adaptive Dead Time
(AST)
The SiC779 has an internal adaptive logic to avoid shoot
through and optimize dead time. The shoot through
protection ensures that both high-side and low-side
MOSFET are not turned on the same time. The adaptive
dead time control operates as follows. When PWM input
goes high the LS gate starts to go low after a few ns. When
this signal crosses through 1.7 V the logic to switch the HS
gate on is activated. When PWM goes low the HS gate goes
low. When the HS gate-to-source drive signal crosses
through 1.7 V the logic to turn on the LS gate is activated.
This feature helps to adjust dead time as gate transitions
change with respect to output current and temperature.
Under Voltage Lockout (UVLO)
During the start up cycle, the UVLO disables the gate drive
holding high-side and low-side MOSFET gate low until the
input voltage rail has reached a point at which the logic
circuitry can be safely activated. The SiC779 also
incorporates logic to clamp the gate drive signals to zero
when the UVLO falling edge triggers the shutdown of the
device. As an added precaution, a 20.2 k resistor is
connected between GH and PHASE to provide a discharge
path for the HS MOSFET.
www.vishay.com
5
Document Number: 67538
S11-0703-Rev. B, 18-Apr-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
Analog electronics
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