BU-61590F5-160Y datasheet, PDF

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BU-61590F5-160Y: DescriptionMil-Std-1553 Controller, 2 Channel(s), 0.125MBps, CMOS, CDFP78, 2.100 X 1.800 INCH, 0.210 INCH HEIGHT, FP-78; CategoryThe embedded processor and controller Microcontrollers and processors; File Size79KB，8 Pages; ManufacturerData Device Corporation

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BU-61590F5-160Y Overview

Mil-Std-1553 Controller, 2 Channel(s), 0.125MBps, CMOS, CDFP78, 2.100 X 1.800 INCH, 0.210 INCH HEIGHT, FP-78

BU-61590F5-160Y Parametric

Parameter Name	Attribute value
Maker	Data Device Corporation
Parts packaging code	DFP
package instruction	2.100 X 1.800 INCH, 0.210 INCH HEIGHT, FP-78
Contacts	78
Reach Compliance Code	unknown
Address bus width	16
boundary scan	NO
maximum clock frequency	16 MHz
letter of agreement	MIL-STD-1553A; MIL-STD-1553B
Data encoding/decoding methods	BIPH-LEVEL(MANCHESTER)
Maximum data transfer rate	0.125 MBps
External data bus width	16
JESD-30 code	R-CDFP-F78
low power mode	NO
Number of serial I/Os	2
Number of terminals	78
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DFP
Package shape	RECTANGULAR
Package form	FLATPACK
Certification status	Not Qualified
Maximum seat height	5.334 mm
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal form	FLAT
Terminal pitch	1.27 mm
Terminal location	DUAL
uPs/uCs/peripheral integrated circuit type	SERIAL IO/COMMUNICATION CONTROLLER, MIL-STD-1553

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BU-61590

MIL-STD-1553A/B AND McAIR BC/RT/MT,

ADVANCED COMMUNICATION ENGINE (ACE)

FEATURES

•

Fully Integrated Terminal

DESCRIPTION

DDC's

BU-61590

BC/RT/MT

Universal Advanced Communication

Engine (ACE) terminal comprises a

complete integrated interface between

a host processor and a MIL-STD-

1553, STANAG 3838, or McAir bus.

The BU-61590 integrates a dual uni-

versal McAir transceiver, protocol,

memory management and processor

interface logic, and 4K words of inter-

nal buffered RAM in either a 78-pin

DIP or flat pack package.

This dual universal transceiver provides

a sinusoidal waveform for full compli-

ance with 1553A, 1553B, and McAir

A3818, A5232, and A5690 standards.

To minimize board space and "glue"

logic, the Universal ACE terminals

provide the ultimate flexibility in inter-

facing to a host processor and inter-

nal/external RAM.

The BU-61590 provides complete

multiprotocol support of MIL-STD-

1553A, 1553B Notice 2, McAir A3818,

A5232,

and

A5690,

General

Dynamics

16PP303,

Grumman

SPG151A, and STANAG 3838 (includ-

ing EFAbus). The advanced functional

architecture of the ACE terminals pro-

vides software compatibility to DDC's

previous AIM series hybrids. In addi-

tion, the ACE Terminals incorporate a

multiplicity of architectural enhance-

ments allowing flexible operation while

off-loading the host processor, ensur-

ing data consistency, and supporting

bulk data transfers.

The BU-61590 may be operated at

either 12 or 16 MHz. Options allow for

a hardwired or programmable RT

address.

The BU-61590 operates over the full

military temperature range of -55 to

+125°C. Available screened to MIL-

PRF-38534, the terminals are ideal

for demanding military and industrial

processor-to-1553 applications.

•

Dual Universal Transceiver

Satisfies McAir and 1553A/B

•

Multiprotocol Supports:

MIL-STD-1553A and B Notice 2

McAir A3818, A5232, & A5690

General Dynamics 16PP303

(F16) Grumman SPG151A

•

4K x 16 Internal RAM

•

Flexible Processor/Memory

Interface

•

Automatic BC Retries

•

Programmable BC Gap Times

•

BC Frame Auto-Repeat

•

Flexible RT Data Buffering

•

Programmable Illegalization

•

Selective Message Monitor

•

Simultaneous RT/Monitor Mode

TX/RX_A

4K X 16

SHARED

RAM

TRANSCEIVER

DATA

BUFFERS

PROCESSOR

DATA BUS

CH. A

TX/RX_A

DATA BUS

DUAL

ENCODER/DECODER,

MULTIPROTOCOL

AND

MEMORY

MANAGEMENT

D15-D0

TX/RX_B

ADDRESS BUS

ADDRESS

BUFFERS

A15-A0

PROCESSOR

ADDRESS BUS

CH. B

TRANSCEIVER

TX/RX_B

PROCESSOR

AND

MEMORY

INTERFACE

LOGIC

TRANSPARENT/BUFFERED, STRBD, SELECT,

RD/WR, MEM/REG, TRIGGER_SEL/MEMENA-IN,

MSB/LSB/DTGRT, INT_ACK

IOEN, MEMENA-OUT, READYD

ADDR_LAT/MEMOE, ZERO_WAIT/MEMWR,

8/16-BIT/DTREQ, POLARITY_SEL/DTACK

INT

PROCESSOR

AND

MEMORY

CONTROL

INTERRUPT

REQUEST

RT ADDRESS

RTAD4-RTAD0, RTADP

INCMD

MISCELLANEOUS

CLK_IN, TAG_CLK, BC/MT_ENA, TX_INH_A, TX_INH_B,

MSTCLR, SSFLAG/EXT_TRG, ILLEGAL, RT_AD_LAT

BU-61590 BLOCK DIAGRAM

1994, 1999 Data Device Corporation

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