DS1248P datasheet, PDF - EEWORLD Datasheet

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DS1248P: Description1024k NV SRAM with Phantom Clock; File Size524KB，19 Pages; ManufacturerMaxim; Websitehttps://www.maximintegrated.com/en.html

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DS1248P Overview

1024k NV SRAM with Phantom Clock

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19-6078; Rev 11/11

1024K NV SRAM with Phantom Clock

FEATURES



DS1248/DS1248P

Real-Time Clock (RTC) Keeps Track of

Hundredths of Seconds, Minutes, Hours,

Days, Date of the Month, Months, and Years

128K x 8 NV SRAM Directly Replaces

Volatile Static RAM or EEPROM

Embedded Lithium Energy Cell Maintains

Calendar Operation and Retains RAM Data

Watch Function is Transparent to RAM

Operation

Automatic Leap Year Compensation Valid

Up to 2100

Full 10% Operating Range

Over 10 Years of Data Retention in the

Absence of Power

Lithium Energy Source is Electrically

Disconnected to Retain Freshness Until

Power is Applied for the First Time

DIP Module Only

Standard 32-Pin JEDEC Pinout

PIN CONFIGURATIONS

TOP VIEW

RST

A16

A14

A12

DQ0

DQ1

DQ2

GND

DS1248

A15

N.C.

A13

A11

A10

DQ7

DQ6

DQ5

DQ4

DQ3



Encapsulated DIP

(740-mil Flush)



Underwriters Laboratories (UL) Recognized

(www.maxim-ic.com/qa/info/ul/)

PowerCap Module Board Only

Surface Mountable Package for Direct

Connection to PowerCap Containing

Battery and Crystal

Replaceable Battery (PowerCap)

Pin-for-Pin Compatible with DS1244P and

DS1251P

RST

A15

A16

N.C.

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

GND

DS1248P

GND

BAT

N.C.

A14

A13

A12

A11

A10

PowerCap Module Board

(Uses DS9034PCX+ PowerCap)

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DS1248/DS1248P 1024K NV SRAM with Phantom Clock

PHANTOM CLOCK OPERATION

Communication with the phantom clock is established by pattern recognition on a serial bit stream of

64 bits, which must be matched by executing 64 consecutive write cycles containing the proper data on

DQ0. All accesses that occur prior to recognition of the 64-bit pattern are directed to memory.

After recognition is established, the next 64 read or write cycles either extract or update data in the

phantom clock, and memory access is inhibited.

Data transfer to and from the timekeeping function is accomplished with a serial bit stream under control

of chip enable, output enable, and write enable. Initially, a read cycle to any memory location using the

and

control of the phantom clock starts the pattern recognition sequence by moving a pointer to

the first bit of the 64-bit comparison register. Next, 64 consecutive write cycles are executed using the

and

control of the SmartWatch. These 64 write cycles are used only to gain access to the phantom

clock. Therefore, any address to the memory in the socket is acceptable. However, the write cycles

generated to gain access to the phantom clock are also writing data to a location in the mated RAM. The

preferred

way

manage

this

requirement

set

aside

just

one address location in RAM as a phantom clock scratch pad. When the first write cycle is executed, it is

compared to bit 0 of the 64-bit comparison register. If a match is found, the pointer increments to the next

location of the comparison register and awaits the next write cycle. If a match is not found, the pointer

does not advance and all subsequent write cycles are ignored. If a read cycle occurs at any time during

pattern recognition, the present sequence is aborted and the comparison register pointer is reset. Pattern

recognition continues for a total of 64 write cycles as described above until all the bits in the comparison

data transfer to or from the timekeeping registers can proceed. The next 64 cycles will cause the phantom

clock to either receive or transmit data on DQ0, depending on the level of the

pin or the

pin.

Cycles to other locations outside the memory block can be interleaved with

cycles without

interrupting the pattern recognition sequence or data transfer sequence to the phantom clock.

PHANTOM CLOCK REGISTER INFORMATION

The phantom clock information is contained in eight registers of 8 bits, each of which is sequentially

accessed 1 bit at a time after the 64-bit pattern recognition sequence has been completed. When updating

the phantom clock registers, each register must be handled in groups of 8 bits. Writing and reading

individual bits within a register could produce erroneous results. These read/write registers are defined in

Figure 2.

Data contained in the phantom clock register is in binary-coded decimal format (BCD). Reading and

writing the registers is always accomplished by stepping through all eight registers, starting with bit 0 of

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DS1248P Related Products

	DS1248P	DS1248
Description	1024k NV SRAM with Phantom Clock	1024k NV SRAM with Phantom Clock

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