LPC11U2x
32-bit ARM Cortex-M0 microcontroller; up to 32 kB flash; up
to 10 kB SRAM and 4 kB EEPROM; USB device; USART
Rev. 1 — 29 November 2011
Preliminary data sheet
1. General description
The LPC11U2x are a ARM Cortex-M0 based, low-cost 32-bit MCU family, designed for
8/16-bit microcontroller applications, offering performance, low power, simple instruction
set and memory addressing together with reduced code size compared to existing 8/16-bit
architectures.
The LPC11U2x operate at CPU frequencies of up to 50 MHz.
Equipped with a highly flexible and configurable Full-Speed USB 2.0 device controller, the
LPC11U2x brings unparalleled design flexibility and seamless integration to today’s
demanding connectivity solutions.
The peripheral complement of the LPC11U2x includes up to 32 kB of flash memory, up to
10 kB of SRAM data memory and 4 kB EEPROM, one Fast-mode Plus I
2
C-bus interface,
one RS-485/EIA-485 USART with support for synchronous mode and smart card
interface, two SSP interfaces, four general-purpose counter/timers, a 10-bit ADC
(Analog-to-Digital Converter), and up to 54 general-purpose I/O pins.
2. Features and benefits
System:
ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.
ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).
Non-Maskable Interrupt (NMI) input selectable from several input sources.
System tick timer.
Memory:
Up to 32 kB on-chip flash program memory.
Up to 4 kB on-chip EEPROM data memory; byte erasable and byte programmable.
Up to 10 kB SRAM data memory.
16 kB boot ROM.
In-System Programming (ISP) and In-Application Programming (IAP) for flash and
EEPROM via on-chip bootloader software.
ROM-based USB drivers. Flash updates via USB supported.
ROM-based 32-bit integer division routines.
Debug options:
Standard JTAG (Joint Test Action Group) test interface for BSDL (Boundary Scan
Description Language).
Serial Wire Debug.
NXP Semiconductors
LPC11U2x
32-bit ARM Cortex-M0 microcontroller
Digital peripherals:
Up to 54 General-Purpose I/O (GPIO) pins with configurable pull-up/pull-down
resistors, repeater mode, and open-drain mode.
Up to 8 GPIO pins can be selected as edge and level sensitive interrupt sources.
Two GPIO grouped interrupt modules enable an interrupt based on a
programmable pattern of input states of a group of GPIO pins.
High-current source output driver (20 mA) on one pin.
High-current sink driver (20 mA) on true open-drain pins.
Four general-purpose counter/timers with a total of up to 5 capture inputs and 13
match outputs.
Programmable Windowed WatchDog Timer (WWDT) with a dedicated, internal
low-power WatchDog Oscillator (WDO).
Analog peripherals:
10-bit ADC with input multiplexing among eight pins.
Serial interfaces:
USB 2.0 full-speed device controller.
USART (Universal Synchronous Asynchronous Receiver/Transmitter) with
fractional baud rate generation, internal FIFO, a full modem control handshake
interface, and support for RS-485/9-bit mode and synchronous mode. USART
supports an asynchronous smart card interface (ISO 7816-3).
Two SSP (Synchronous Serial Port) controllers with FIFO and multi-protocol
capabilities.
I
2
C-bus interface supporting the full I
2
C-bus specification and Fast-mode Plus with
a data rate of up to 1 Mbit/s with multiple address recognition and monitor mode.
Clock generation:
Crystal Oscillator with an operating range of 1 MHz to 25 MHz (system oscillator).
12 MHz high-frequency Internal RC oscillator (IRC) that can optionally be used as
a system clock.
Internal low-power, low-frequency WatchDog Oscillator (WDO) with programmable
frequency output.
PLL allows CPU operation up to the maximum CPU rate with the system oscillator
or the IRC as clock sources.
A second, dedicated PLL is provided for USB.
Clock output function with divider that can reflect the crystal oscillator, the main
clock, the IRC, or the watchdog oscillator.
Power control:
Integrated PMU (Power Management Unit) to minimize power consumption during
Sleep, Deep-sleep, Power-down, and Deep power-down modes.
Power profiles residing in boot ROM allow optimized performance and minimized
power consumption for any given application through one simple function call.
Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep
power-down.
Processor wake-up from Deep-sleep and Power-down modes via reset, selectable
GPIO pins, watchdog interrupt, or USB port activity.
Processor wake-up from Deep power-down mode using one special function pin.
Power-On Reset (POR).
Brownout detect with four separate thresholds for interrupt and forced reset.
LPC11U2X
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Preliminary data sheet
Rev. 1 — 29 November 2011
2 of 67
NXP Semiconductors
LPC11U2x
32-bit ARM Cortex-M0 microcontroller
Unique device serial number for identification.
Single 3.3 V power supply (1.8 V to 3.6 V).
Temperature range
40 C
to +85
C.
Available as LQFP64, LQFP48, TFBGA48, and HVQFN33 package.
3. Applications
Consumer peripherals
Medical
Industrial control
Handheld scanners
USB audio devices
4. Ordering information
Table 1.
Ordering information
Package
Name
LPC11U23FBD48/301
LPC11U24FHI33/301
LPC11U24FBD48/301
LPC11U24FET48/301
LPC11U24FHN33/401
LPC11U24FBD48/401
LPC11U24FBD64/401
LQFP48
HVQFN33
LQFP48
TFBGA48
HVQFN33
LQFP48
LQFP64
Description
plastic low profile quad flat package; 48 leads; body 7
7
1.4 mm
plastic thermal enhanced very thin quad flat package; no leads; 33
terminals; body 5
5
0.85 mm
plastic low profile quad flat package; 48 leads; body 7
7
1.4 mm
plastic thin fine-pitch ball grid array package; 48 balls; body 4.5
4.5
0.7 mm
plastic thermal enhanced very thin quad flat package; no leads; 33
terminals; body 7
7
0.85 mm
plastic low profile quad flat package; 48 leads; body 7
7
1.4 mm
plastic low profile quad flat package; 64 leads; body 10
10
1.4 mm
Version
SOT313-2
n/a
SOT313-2
SOT1155-2
n/a
SOT313-2
SOT314-2
Type number
4.1 Ordering options
Table 2.
Part ordering options
Flash EEPROM Main
USB
USB I
2
C-bus SSP ADC
GPIO Package
(kB) (kB)
SRAM SRAM
FM+
channels
(kB)
(kB)
1
2
2
2
4
4
4
6
6
6
6
8
8
8
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
8
8
8
8
8
8
8
40
26
40
40
26
40
54
LQFP48
HVQFN33 (5
5 )
LQFP48
TFBGA48
HVQFN33 (7
7)
LQFP48
LQFP64
32
32
Part Number
LPC11U23FBD48/301 24
LPC11U24FHI33/301
LPC11U24FET48/301
LPC11U24FBD48/301 32
LPC11U24FHN33/401 32
LPC11U24FBD48/401 32
LPC11U24FBD64/401 32
LPC11U2X
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Preliminary data sheet
Rev. 1 — 29 November 2011
3 of 67
NXP Semiconductors
LPC11U2x
32-bit ARM Cortex-M0 microcontroller
5. Block diagram
SWD, JTAG
XTALIN XTALOUT
RESET
LPC11U2x
TEST/DEBUG
INTERFACE
SYSTEM OSCILLATOR
IRC, WDO
BOD
POR
PLL0
USB PLL
CLOCK
GENERATION,
POWER CONTROL,
SYSTEM
FUNCTIONS
CLKOUT
ARM
CORTEX-M0
system bus
EEPROM
1/2/4 kB
FLASH
24/32 kB
slave
SRAM
8/10 kB
slave
ROM
16 kB
slave
master
slave
USB DEVICE
CONTROLLER
USB_DP
USB_DM
USB_VBUS
USB_FTOGGLE,
USB_CONNECT
GPIO ports 0/1
HIGH-SPEED
GPIO
slave
AHB-LITE BUS
slave
AHB TO APB
BRIDGE
USART/
SMARTCARD INTERFACE
10-bit ADC
I
2
C-BUS
16-bit COUNTER/TIMER 0
SSP0
16-bit COUNTER/TIMER 1
32-bit COUNTER/TIMER 0
32-bit COUNTER/TIMER 1
SYSTEM CONTROL
WINDOWED WATCHDOG
TIMER
PMU
SSP1
IOCON
RXD
TXD
DCD, DSR
(1)
, RI
(1)
CTS, RTS, DTR
SCLK
CT16B0_MAT[1:0]
CT16B0_CAP0
CT16B1_MAT[1:0]
CT16B1_CAP0
CT32B0_MAT[3:0]
CT32B0_CAP0
CT32B1_MAT[3:0]
CT32B1_CAP[1:0]
(2)
AD[7:0]
SCL, SDA
SCK0, SSEL0,
MISO0, MOSI0
SCK1, SSEL1,
MISO1, MOSI1
GPIO pins
GPIO pins
GPIO pins
GPIO INTERRUPTS
GPIO GROUP0 INTERRUPTS
GPIO GROUP1 INTERRUPTS
002aag333
(1) Not available on HVQFN33 packages.
(2) CT32B1_CAP1 available in TFBGA48 only.
Fig 1.
Block diagram
LPC11U2X
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Preliminary data sheet
Rev. 1 — 29 November 2011
4 of 67
NXP Semiconductors
LPC11U2x
32-bit ARM Cortex-M0 microcontroller
6. Pinning information
6.1 Pinning
PIO0_16/AD5/CT32B1_MAT3/WAKEUP
26
terminal 1
index area
PIO1_19/DTR/SSEL1
RESET/PIO0_0
PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE
XTALIN
XTALOUT
V
DD
PIO0_20/CT16B1_CAP0
PIO0_2/SSEL0/CT16B0_CAP0
1
2
3
4
5
6
7
8
32
31
30
29
28
27
25
24
23
22
SWDIO/PIO0_15/AD4/CT32B1_MAT2
PIO1_15/DCD/CT16B0_MAT2/SCK1
PIO0_17/RTS/CT32B0_CAP0/SCLK
PIO0_18/RXD/CT32B0_MAT0
PIO0_19/TXD/CT32B0_MAT1
PIO0_23/AD7
V
DD
TRST/PIO0_14/AD3/CT32B1_MAT1
TDO/PIO0_13/AD2/CT32B1_MAT0
TMS/PIO0_12/AD1/CT32B1_CAP0
TDI/PIO0_11/AD0/CT32B0_MAT3
PIO0_22/AD6/CT16B1_MAT1/MISO1
SWCLK/PIO0_10/SCK0/CT16B0_MAT2
PIO0_9/MOSI0/CT16B0_MAT1
PIO0_8/MISO0/CT16B0_MAT0
LPC11U24
21
20
19
33 V
SS
10
11
12
13
14
15
PIO0_6/USB_CONNECT/SCK0
16
PIO0_7/CTS
9
18
17
USB_DM
PIO0_3/USB_VBUS
PIO0_4/SCL
PIO0_5/SDA
PIO0_21/CT16B1_MAT0/MOSI1
USB_DP
002aag621
Transparent top view
Fig 2.
Pin configuration (HVQFN33)
LPC11U2X
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Preliminary data sheet
Rev. 1 — 29 November 2011
5 of 67
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