DS1216 datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > DS1216

Preview

DS1216: DescriptionSmartWatch RAM DS1216B/C/D/H SmartWatch ROM DS1216E/F; File Size600KB，15 Pages; ManufacturerMaxim; Websitehttps://www.maximintegrated.com/en.html

Download Datasheet View All

DS1216 Overview

SmartWatch RAM DS1216B/C/D/H SmartWatch ROM DS1216E/F

Preview

Download Datasheet

View All

19-6075; Rev 11/11

SmartWatch RAM (DS1216B/C/D/H);

SmartWatch ROM (DS1216E/F)

GENERAL DESCRIPTION

The DS1216 SmartWatch RAM and SmartWatch

ROM sockets are 600-mil-wide DIP sockets with a

built-in CMOS watch function, an NV RAM

controller circuit, and an embedded lithium energy

source. The sockets provide an NV RAM solution

for memory sized from 2K x 8 to 512K x 8 with

package sizes from 26 pins to 32 pins. When a

socket is mated with a CMOS SRAM, it provides a

complete solution to problems associated with

memory volatility and uses a common energy

source to maintain time and date. The SmartWatch

ROM sockets use the embedded lithium source to

maintain the time and date only. A key feature of

the SmartWatch is that the watch function remains

transparent to the RAM. The SmartWatch monitors

for an out-of-tolerance condition. When such a

condition occurs, an internal lithium energy source

is automatically switched on and write protection

is unconditionally enabled to prevent loss of watch

and RAM data.

DS1216

FEATURES



Keeps Track of Hundredths of Seconds,

Seconds, Minutes, Hours, Days, Date of the

Month, Months, and Years

Converts Standard 2K x 8 Up to 512K x 8

CMOS Static RAMs into Nonvolatile Memory

Embedded Lithium Energy Cell Maintains

Watch Information and Retains RAM Data

Watch Function is Transparent to RAM

Operation

Automatic Leap Year Compensation Valid Up

to 2100

Lithium Energy Source is Electrically

Disconnected to Retain Freshness Until Power

is Applied for the First Time

Proven Gas-Tight Socket Contacts

Full

±10%

Operating Range

Accuracy Better Than

±1

Minute/Month

at +25°C



TYPICAL OPERATING CIRCUIT

ORDERING INFORMATION

PART

DS1216B

DS1216C

DS1216D

DS1216E

DS1216F

DS1216H

TEMP RANGE

0°C to +70°C

PIN-PACKAGE

28 SmartWatch Socket

32 SmartWatch Socket

28 SmartWatch Socket

32 SmartWatch Socket

(See Figure 2 for letter suffix marking identification.)

Selector Guide appears on page 2.

1 of 15

DS1216 SmartWatch RAM/SmartWatch ROM

DETAILED DESCRIPTION

The DS1216 SmartWatch RAM and SmartWatch ROM Sockets are 600-mil-wide DIP sockets with a

built-in CMOS watch function, an NV RAM controller circuit, and an embedded lithium energy source.

The sockets provide an NV RAM solution for memory sized from 2K x 8 to 512K x 8 with package sizes

from 26 pins to 32 pins. When a socket is mated with a CMOS SRAM, it provides a complete solution to

problems associated with memory volatility and uses a common energy source to maintain time and date.

The SmartWatch ROM sockets use the embedded lithium source to maintain the time and date only. A

key feature of the SmartWatch is that the watch function remains transparent to the RAM. The

SmartWatch monitors V

for an out-of-tolerance condition. When such a condition occurs, an internal

lithium energy source is automatically switched on and write protection is unconditionally enabled to

prevent loss of watch and RAM data.

Using the SmartWatch saves PC board space since the combination of SmartWatch and the mated RAM

take up no more area than the memory alone. The SmartWatch uses the V

, data I/O 0,

CE, OE,

and

for RAM and watch control. All other pins are passed straight through to the socket receptacle.

The SmartWatch provides timekeeping information including hundredths of seconds, seconds, minutes,

hours, days, date, months, and years. The date at the end of the month is automatically adjusted for

months with fewer than 31 days, including correction for leap years. The SmartWatch operates in either

24-hour or 12-hour format with an AM/PM indicator.

OPERATION

Communication with the SmartWatch RAM is established by pattern recognition on a serial bit stream of

64 bits that must be matched by executing 64 consecutive write cycles containing the proper data on

DQ0. On the SmartWatch ROM, communication with the clock is established using A2 and A0, and

either

CE.

All accesses that occur prior to recognition of the 64-bit pattern are directed to memory.

After the pattern match, the next 64 reads and/or writes are directed to the clock, and the RAM is

disabled. Once the pattern is established, the next 64 read/write cycles will be directed to the RTC

registers. When power is cycled, 64 reads should be executed prior to any writes to ensure that the RTC

registers are not written. A pattern match is ignored if the

RST

bit is zero and the

RST

pin goes low

during the match sequence. A pattern match is also terminated if a read occurs during the 64-bit match

sequence.

PATTERN MATCH—RAM

Data transfer to and from the timekeeping registers is accomplished with a serial bit stream under control

of chip enable (CE), output enable (OE), and write enable (WE). Initially, a read cycle to any memory

location using the

and

control of the SmartWatch starts the pattern recognition sequence by

moving a pointer to the first bit of the 64-bit comparison register. Next, 64 consecutive write cycles are

executed using the

and

control of the SmartWatch. These 64 write cycles are used only to gain

access to the SmartWatch. Therefore, any address to the memory in the socket is acceptable. However,

the write cycles generated to gain access to the SmartWatch are also writing data to a location in the

mated RAM. The preferred way to manage this requirement is to set aside just one address location in

RAM as a SmartWatch scratch pad. When the first write cycle is executed, it is compared to bit 0 of the

64-bit comparison register. If a match is found, the pointer increments to the next location of the

3 of 15

DS1216 SmartWatch RAM/SmartWatch ROM

comparison register and awaits the next write cycle. If a match is not found, the pointer does not advance

and all subsequent write cycles are ignored. If a read cycle occurs at any time during pattern recognition,

the present sequence is aborted and the comparison register pointer is reset. Pattern recognition continues

for 64 write cycles as described above until all the bits in the comparison register have been matched (this

bit pattern is shown in Figure 1). With a correct match for 64 bits, the SmartWatch is enabled and data

transfer to or from the timekeeping registers can proceed. The next 64 cycles will cause the SmartWatch

to either receive or transmit data on DQ0, depending on the level of the

pin or the

pin. Cycles to

other locations outside the memory block can be interleaved with

cycles without interrupting the

pattern recognition sequence or data transfer sequence to the SmartWatch.

PATTERN MATCH—ROM

Communication with the SmartWatch is established by pattern recognition of a serial bit stream of 64 bits

that must be matched by executing 64 consecutive write cycles, placing address bit A2 low with the

proper data on address bit A0. The 64 write cycles are used only to gain access to the SmartWatch. Prior

to executing the first of 64 write cycles, a read cycle should be executed by holding A2 high. The read

cycle will reset the comparison register pointer within the SmartWatch, ensuring the pattern recognition

starts with the first bit of the sequence. When the first write cycle is executed, it is compared to bit 0 of

the 64-bit comparison register. If a match is found, the pointer increments to the next location of the

comparison register and awaits the next write cycle. If a match is not found, the pointer does not advance

and all subsequent write cycles are ignored. If a read cycle occurs at any time during pattern recognition,

the present sequence is aborted and the comparison register pointer is reset. Pattern recognition continues

for a total of 64 write cycles as described above, until all the bits in the comparison register have been

matched (this bit pattern is shown in Figure 1). With a correct match for 64 bits, the SmartWatch is

enabled and data transfer to or from the timekeeping registers can proceed. The next 64 cycles will cause

the SmartWatch to either receive data on data in (A0) or transmit data on data out (DQ0), depending on

the level of /WRITE READ (A2).

After power-up, the controller could be in the 64-bit clock register read/write sequence (from an

incomplete access prior to power-down). Therefore, it is recommended that a 64-bit read be performed

upon power-up to prevent accidental writes to the clock, and to prevent reading clock data when access to

the RAM would otherwise be expected.

4 of 15

Recommended Resources

PCB board interconnection method

Thyristor AC switch circuit 3b

Single button control on-off relay circuit 4

LR7 typical application circuit diagram

Application circuit of Shuanghua JDB02 distribution current transformer

Tricycle steering sounder

I would like to ask about the MSP430 parallel port JTAG emulator problem.: I have two parallel port JTAG emulators. One is non-isolated, and the other is isolated. I have already selected the LPT mode as EPP/ECP mode in the Bios. My target board power supply is 3.3V, and the...; zhouliyong11 Embedded System

Not a valid Windows CE application?: I used the vs2008 wizard to generate a program, selected wince, cf2.0, only one form, no code written. When I run it on wince5.0, it prompts: It is not a valid wince program. I have installed cf2.0. L...; gga Embedded System

Students who have never visited an electronics market, please pay attention!: Hehe, I saw a post on the Internet that said something with pictures and texts. I would like to share it with you: These are various triodes (transistors), some of which are older than me...This germa...; john_wang Analog electronics

[Start at 10:30] Interpretation of TI's latest smart lock, visual doorbell, and network camera solutions, and recommendations for its core components: Today, two experienced technical sales engineers from TI will give a live talk on smart buildings (I guess they are crosstalk performers who were delayed by the electronics industry) : -Analysis of po...; nmg TI Technology Forum

Questions about spi: When I was doing SPI communication of ad7280a, I found that it receives data on the falling edge and sends data on the rising edge.The PIC microcontroller I chose only hasas shown in the figure: In ot...; sjl2001 ADI Reference Circuit

Recruiting equipment maintenance engineers: Recruiting instrument maintenance engineers: Experience in computer motherboard chip-level maintenance, college degree or above in electronics. Strong hands-on learning ability is required. 2 Recruiti...; wht19823 Recruitment

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components