DS1244 datasheet, PDF - EEWORLD Datasheet

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DS1244: DescriptionLow-Power, 24-Bit ANALOG-TO-DIGITAL CONVERTER; File Size533KB，20 Pages; ManufacturerMaxim; Websitehttps://www.maximintegrated.com/en.html

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DS1244 Overview

Low-Power, 24-Bit ANALOG-TO-DIGITAL CONVERTER

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19-6077; Rev 11/11

www.maxim-ic.com

DS1244/DS1244P

256K NV SRAM with Phantom Clock

PIN CONFIGURATIONS

TOP VIEW

A14/RST

A12

DQ0

DQ1

DQ2

GND

A13

A11

A10

DQ7

DQ6

DQ5

DQ4

DQ3

FEATURES



Real-Time Clock (RTC) Keeps Track of

Hundredths of Seconds, Minutes, Hours,

Days, Date of the Month, Months, and Years

32K x 8 NV SRAM Directly Replaces

Volatile Static RAM or EEPROM

Embedded Lithium Energy Cell Maintains

Calendar Operation and Retains RAM Data

Watch Function is Transparent to RAM

Operation

Automatic Leap Year Compensation Valid

Up to 2100

Full 10% Operating Range

Over 10 Years of Data Retention in the

Absence of Power

Lithium Energy Source is Electrically

Disconnected to Retain Freshness Until

Power is Applied for the First Time

DIP Module Only

Standard 28-Pin JEDEC Pinout

PowerCap Module Board Only

– Surface Mountable Package for Direct

Connection to PowerCap Containing

Battery and Crystal

– Replaceable Battery (PowerCap)

– Pin-for-Pin Compatible with DS1248P

and DS1251P

Underwriters Laboratories (UL) Recognized

DS1244

EDIP Module

(740 mils)

RST

N.C.

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

GND

DS1244P

GND V

BAT

N.C.

A14

A13

A12

A11

A10

PowerCap Module

(Uses DS9034PCX+ PowerCap)

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DS1244/DS1244P

The DS1244 256K NV SRAM with a Phantom clock is a fully static nonvolatile RAM (NV SRAM)

(organized as 32K words by 8 bits) with a built-in real-time clock. The DS1244 has a self-contained

lithium energy source and control circuitry, which constantly monitors V

for an out-of-tolerance

condition. When such a condition occurs, the lithium energy source is automatically switched on and

write protection is unconditionally enabled to prevent garbled data in both the memory and real-time

clock.

The phantom clock provides timekeeping information for hundredths of seconds, seconds, minutes, hours,

days, date, months, and years. The date at the end of the month is automatically adjusted for months with

fewer than 31 days, including correction for leap years. The phantom clock operates in either 24-hour or

12-hour format with an AM/PM indicator.

DESCRIPTION

PACKAGES

The DS1244 is available in two packages: 28-pin encapsulated DIP and 34-pin PowerCap module. The

28-pin DIP-style module integrates the crystal, lithium energy source, and silicon all in one package. The

34-pin PowerCap module board is designed with contacts for connection to a separate PowerCap

(DS9034PCX) that contains the crystal and battery. This design allows the PowerCap to be mounted on

top of the DS1244P after the completion of the surface mount process. Mounting the PowerCap after the

surface mount process prevents damage to the crystal and battery due to the high temperatures required

for solder reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap module board and

PowerCap are ordered separately and shipped in separate containers. The part number for the PowerCap

is DS9034PCX.

The DS1244 executes a read cycle whenever

(write enable) is inactive (high) and

(chip enable)

is active (low). The unique address specified by the 15 address inputs (A0–A14) defines which of the

32,768 bytes of data is to be accessed. Valid data is available to the eight data-output drivers within t

ACC

(access time) after the last address input signal is stable, providing that

and

(output enable)

access times and states are also satisfied. If

and

access times are not satisfied, then data access

must be measured from the later occurring signal (

) and the limiting parameter is either t

for

CE or t

for OE , rather than address access.

RAM READ MODE

The DS1244 is in the write mode whenever the WE and CE signals are in the active (low) state after

address inputs are stable. The latter occurring falling edge of

will determine the start of the

write cycle. The write cycle is terminated by the earlier rising edge of

. All address inputs

must be kept valid throughout the write cycle.

must return to the high state for a minimum recovery

time (t

) before another cycle can be initiated. The

control signal should be kept inactive (high)

during write cycles to avoid bus contention. However, if the output bus has been enabled (

and

active) then WE will disable the outputs in t

ODW

from its falling edge.

RAM WRITE MODE

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