19-4931; Rev 4; 1/12
Single-Channel 1-Wire Master with Sleep Mode
General Description
The DS2482-101 is an I
2
C-to-1-Wire
®
bridge device
that interfaces directly to standard (100kHz max) or fast
(400kHz max) I
2
C masters to perform bidirectional pro-
tocol conversion between the I
2
C master and any
downstream 1-Wire slave devices. Relative to any
attached 1-Wire slave device, the DS2482-101 is a
1-Wire master. Internal, factory-trimmed timers relieve
the system host processor from generating time-critical
1-Wire waveforms, supporting both standard and over-
drive 1-Wire communication speeds. To optimize
1-Wire waveform generation, the DS2482-101 performs
slew-rate control on rising and falling 1-Wire edges and
provides additional programmable features to match
drive characteristics to the 1-Wire slave environment.
Programmable, strong pullup features support 1-Wire
power delivery to 1-Wire devices such as EEPROMs
and sensors. The DS2482-101 combines these features
with an output to control an external MOSFET for
enhanced strong pullup application. The I
2
C slave
address assignment is controlled by one binary
address input, resolving potential conflicts with other
I
2
C slave devices in the system. When not in use, the
device can be put in sleep mode where power con-
sumption is minimal.
Features
♦
I
2
C Host Interface Supports 100kHz and 400kHz
I
2
C Communication Speeds
♦
1-Wire Master IO with Selectable Active or
Passive 1-Wire Pullup
♦
Provides Reset/Presence, 8-Bit, Single-Bit, and
3-Bit 1-Wire IO Sequences
♦
Standard and Overdrive 1-Wire Communication
Speeds
♦
Slew-Controlled 1-Wire Edges
♦
Strong 1-Wire Pullup Provided by an Internal Low-
Impedance Signal Path
♦
PCTLZ Output to Optionally Control an External
MOSFET for Stronger Pullup Requirements
♦
Supports Power-Saving Sleep Mode
♦
One Address Input for I
2
C Address Assignment
♦
Operating Range: 2.9V to 5.5V, -40°C to +85°C
♦
9-Bump WLP Package
DS2482-101
Ordering Information
PART
DS2482X-101+T
TEMP RANGE
-40°C to +85°C
PIN-PACKAGE
9 WLP (2.5k pieces)
Applications
Printers
Medical Instruments
Industrial Sensors
Cell Phones, PDAs
+Denotes
a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
Pin Configurations appear at end of data sheet.
Typical Operating Circuit
V
CC
R
P
*
(I
2
C PORT)
μC
SDA
SCL
OPTIONAL
CIRCUITRY
PCTLZ
BSS84
DS2482-101
SLPZ
AD0
IO
1-Wire LINE
1-Wire
DEVICE
1-Wire
DEVICE
1-Wire
DEVICE
*R
P
= I
2
C PULLUP RESISTOR (SEE THE
APPLICATIONS INFORMATION
SECTION FOR R
P
SIZING).
1-Wire is a registered trademark of Maxim Integrated Products, Inc.
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Single-Channel 1-Wire Master with Sleep Mode
DS2482-101
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground.........-0.5V to +6V
Maximum Current into Any Pin..........................................±20mA
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-55°C to +125°C
Soldering Temperature (reflow) .......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
CC
= 2.9V to 5.5V, T
A
= -40°C to +85°C.)
PARAMETER
Supply Voltage
Supply Current
1-Wire Input High (Notes 2, 3)
1-Wire Input Low (Notes 2, 3)
1-Wire Weak Pullup Resistor
1-Wire Output Low
Active Pullup On Time
(Notes 4, 5)
Strong Pullup Voltage Drop
SYMBOL
V
CC
I
CC
V
IH1
V
IL1
R
WPU
V
OL1
t
APUOT
V
STRPU
CONDITIONS
3.3V
5V
(Note 1)
Sleep mode (SLPZ low), V
CC
= 5.5V
3.3V
5V
3.3V
5V
(Note 4)
At 4mA load
Standard
Overdrive
V
CC
3.2V, 1.5mA load
V
CC
5.2V, 3mA load
Standard (3.3V
±10%)
Overdrive (3.3V
±10%)
Standard (5.0V
±10%)
Overdrive (5.0V
±10%)
Standard (3.3V
±10%)
Overdrive (3.3V
±10%)
Standard (5.0V
±10%)
Overdrive (5.0V
±10%)
MIN
2.9
4.5
TYP
3.3
5.0
0.5
1.9
3.4
0.9
1.2
1675
0.4
2.7
0.6
0.3
0.5
4.2
22.1
6.5
40
4
20
6
31
2.2
8.4
1.1
15
1.8
72.8
11.0
3.0
0.59
2.2
0.44
MAX
3.7
5.5
750
1.0
UNITS
V
μA
V
V
1000
2.3
0.4
2.5
0.5
V
μs
V
Pulldown Slew Rate (Note 6)
PD
SRC
Pullup Slew Rate (Note 6)
PU
SRC
1
5
2
10
0.8
2.7
1.3
3.4
V/μs
V/μs
Power-On Reset Trip Point
V
POR
Standard
Overdrive
Standard
Overdrive
Standard
Overdrive
Standard (3.3V to 0V)
Overdrive (3.3V to 0V)
Standard (5.0V to 0V)
Overdrive (5.0V to 0V)
7.6
0.9
13.3
1.4
65.8
9.9
0.54
0.10
0.55
0.09
8
1
14
1.5
69.3
10.5
V
1-Wire TIMING (Note 5) (See Figures 4, 5, and 6)
Write-One/Read Low Time
Read Sample Time
1-Wire Time Slot
t
W1L
t
MSR
t
SLOT
μs
μs
μs
Fall Time High-to-Low
(Notes 6, 7)
t
F1
μs
2
_______________________________________________________________________________________
Single-Channel 1-Wire Master with Sleep Mode
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= 2.9V to 5.5V, T
A
= -40°C to +85°C.)
PARAMETER
Write-Zero Low Time
Write-Zero Recovery Time
Reset Low Time
Presence-Detect Sample Time
Sampling for Short and Interrupt
Reset High Time
CONTROL PIN (PCTLZ)
Output Low Voltage
Output High Voltage
SLEEP PIN (SLPZ)
V
CC
= 2.9V to 3.7V
Low-Level Input Voltage
V
IL
V
CC
= 4.5V to 5.5V
High-Level Input Voltage
Input Leakage Current
Wakeup Time from Sleep Mode
V
IH
I
I
t
SWUP
Input voltage at pin is between
0.1 x V
CC(MAX)
and 0.9 x V
CC(MAX)
(Notes 8, 9)
-0.5
0.7 ×
V
CC
-0.5
0.25 ×
V
CC
0.22 ×
V
CC
V
CC
+
0.5V
1.0
100
0.25 ×
V
CC
0.22 ×
V
CC
V
CC
+
0.5V
V
OLP
V
OHP
V
CC
= 2.9V, 1.2mA load current
0.4mA load current
V
CC
-
0.5V
0.4
V
V
SYMBOL
t
W0L
t
REC0
t
RSTL
t
MSP
t
SI
t
RSTH
Standard
Overdrive
Standard
Overdrive
Standard
Overdrive
Standard
Overdrive
Standard
Overdrive
Standard
Overdrive
CONDITIONS
MIN
60
7.1
5.0
2.8
570
68.4
66.5
7.1
7.6
0.7
554.8
70.3
TYP
64
7.5
5.3
3.0
600
72
70
7.5
8
0.75
584
74
MAX
68
7.9
5.6
3.2
630
75.6
73.5
7.9
8.4
0.8
613.2
77.7
UNITS
μs
μs
μs
μs
μs
μs
DS2482-101
V
V
μA
μs
I
2
C PINS (SCL, SDA, AD0) (Note 10) (See Figure 9)
V
CC
= 2.9V to 3.7V
Low-Level Input Voltage
V
IL
V
CC
= 4.5V to 5.5V
High-Level Input Voltage
Hysteresis of Schmitt Trigger
Inputs
Low-Level Output Voltage at
3mA Sink Current
Output Fall Time from V
IH(MIN)
to
V
IL(MAX)
with a Bus Capacitance
from 10pF to 400pF
Pulse Width of Spikes That Are
Suppressed by the Input Filter
V
IH
V
HYS
V
OL
-0.5
0.7 ×
V
CC
0.05 ×
V
CC
0.4
-0.5
V
V
V
V
t
OF
60
250
ns
t
SP
SDA and SCL pins only
50
ns
_______________________________________________________________________________________
3
Single-Channel 1-Wire Master with Sleep Mode
DS2482-101
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= 2.9V to 5.5V, T
A
= -40°C to +85°C.)
PARAMETER
Input Current Each Input/Output
Pin with an Input Voltage
Between 0.1 x V
CC(MAX)
and
0.9 x V
CC(MAX)
Input Capacitance
SCL Clock Frequency
Hold Time (Repeated) START
Condition (After this period, the
first clock pulse is generated.)
Low Period of the SCL Clock
High Period of the SCL Clock
Setup Time for a Repeated
START Condition
Data Hold Time
Data Setup Time
Setup Time for STOP Condition
Bus Free Time Between a STOP
and START Condition
Capacitive Load for Each Bus
Line
Oscillator Warmup Time
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
I
I
(Notes 11, 12)
-10
+10
μA
C
I
f
SCL
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
SU:STO
t
BUF
C
B
t
OSCWUP
(Note 11)
0
0.6
1.3
0.6
0.6
(Notes 13, 14)
(Note 15)
250
0.6
1.3
(Note 16)
(Note 8)
10
400
pF
kHz
μs
μs
μs
μs
0.9
μs
ns
μs
μs
400
100
pF
μs
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
Note 15:
Note 16:
Operating current with 1-Wire write-byte sequence followed by continuously reading the Status Register at 400kHz in overdrive.
With standard speed, the total capacitive load of the 1-Wire bus should not exceed 1nF. Otherwise, the passive pullup on
threshold V
IL1
may not be reached in the available time. With overdrive speed, the capacitive load on the 1-Wire bus must
not exceed 300pF.
Active pullup guaranteed to turn on between V
IL1(MAX)
and V
IH1(MIN)
.
Active or resistive pullup choice is configurable.
Except for t
F1
, all 1-Wire timing specifications and t
APUOT
are derived from the same timing circuit. Therefore, if one of
these parameters is found to be off the typical value, it is safe to assume that all these parameters deviate from their typi-
cal value in the same direction and by the same degree.
These values apply at full load, i.e., 1nF at standard speed and 0.3nF at overdrive speed. For reduced load, the pulldown
slew rate is slightly faster.
Fall time high-to-low (t
F1
) is derived from PD
SRC
, referenced from 0.9 x V
CC
to 0.1 x V
CC
.
I
2
C communication should not take place for the max t
OSCWUP
or t
SWUP
time following a power-on reset or a wakeup from
sleep mode.
Guaranteed by design and not production tested.
All I
2
C timing values are referred to V
IH(MIN)
and V
IL(MAX)
levels.
Applies to SDA, SCL, and AD0.
The input/output pins of the DS2482-101 do not obstruct the SDA and SCL lines if V
CC
is switched off.
The DS2482-101 provides a hold time of at least 300ns for the SDA signal (referred to the V
IH(MIN)
of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
The maximum t
HD:DAT
need only be met if the device does not stretch the low period (t
LOW
) of the SCL signal.
A fast-mode I
2
C bus device can be used in a standard-mode I
2
C bus system, but the requirement t
SU:DAT
≥
250ns must
then be met. This is automatically the case if the device does not stretch the low period of the SCL signal. If such a device
does stretch the low period of the SCL signal, it must output the next data bit to the SDA line t
R(MAX)
+ t
SU:DAT
= 1000 +
250 = 1250ns (according to the standard-mode I
2
C bus specification) before the SCL line is released.
C
B
—Total capacitance of one bus line in pF. If mixed with high-speed-mode devices, faster fall times according to
I
2
C-
Bus Specification Version 2.1
are allowed.
4
_______________________________________________________________________________________
Single-Channel 1-Wire Master with Sleep Mode
Pin Description
PIN
A1
A2
A3
B1
B2
B3
C2
C3
NAME
PCTLZ
SLPZ
AD0
SCL
SDA
V
CC
GND
IO
FUNCTION
Active-Low Control Output for an External p-Channel MOSFET. Provides extra power to the 1-Wire line, e.g.,
for use with 1-Wire devices that require a higher current temporarily to operate.
Active-Low Control Input to Activate Low-Power Sleep Mode. This pin should be driven by a push-pull port.
I
2
C Address Input. Must be connected to V
CC
or GND.
I
2
C Serial Clock Input. Must be connected to V
CC
through a pullup resistor.
I
2
C Serial Data Input/Output. Must be connected to V
CC
through a pullup resistor.
Power-Supply Input
Ground Reference
Input/Output Driver for 1-Wire Line
DS2482-101
CONFIGURATION
REGISTER
T-TIME OSC
SDA
SCL
I
2
C
INTERFACE
CONTROLLER
INPUT/OUTPUT
CONTROLLER
LINE
XCVR
IO
PCTLZ
AD0
SLPZ
STATUS
REGISTER
READ DATA
REGISTER
DS2482-101
Figure 1. Block Diagram
Detailed Description
The DS2482-101 is a self-timed 1-Wire master that sup-
ports advanced 1-Wire waveform features including
standard and overdrive speeds, active pullup, and
strong pullup for power delivery. The active pullup
affects rising edges on the 1-Wire side. The strong
pullup function uses the same pullup transistor as the
active pullup, but with a different control algorithm. In
addition, the strong pullup activates the PCTLZ pin,
controlling optional external circuitry to deliver addition-
al power beyond the capabilities of the on-chip pullup
transistor. Once supplied with command and data, the
input/output controller of the DS2482-101 performs
time-critical 1-Wire communication functions such as
reset/presence-detect cycle, read-byte, write-byte, sin-
gle-bit R/W, and triplet for ROM Search, without requir-
ing interaction with the host processor. The host obtains
feedback (completion of a 1-Wire function, presence
pulse, 1-Wire short, search direction taken) through the
Status Register and data through the Read Data
Register. The DS2482-101 communicates with a host
processor through its I
2
C bus interface in standard
mode or in fast mode. The logic state of the address
pin determines the I
2
C slave address of the
DS2482-101, allowing two devices operating on the
same bus segment without requiring a hub. See
Figure 1 for a block diagram.
_______________________________________________________________________________________
5
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