HI-3717
November 2011
Single-Rail ARINC 717 Protocol IC
with SPI Interface
APPLICATIONS
·
·
·
·
Digital Flight Data Acquisition Units (DFDAU)
Digital Flight Data Recorders (DFDR)
Quick Access Recorders (cassette type)
Expandable Flight Data Acquisition and Recording
Systems
GENERAL DESCRIPTION
The HI-3717 from Holt Integrated Circuits is a CMOS device
designed for interfacing an ARINC 717 compatible bus to a
Serial Peripheral Interface (SPI) enabled micro-controller.
The part includes a selectable Harvard Bi-Phase (HBP) or
Bi-Polar Return-to-Zero (BPRZ) receive channel and
transmit channels with HBP and BPRZ encoders and line
drivers. The receive channel has integrated analog line
receivers and the transmit channels have integrated line
drivers for the corresponding encoding method (HBP and
BPRZ). The part operates from a single +3.3V supply using
only four external capacitors. Each transmit and receive
channel has a 32-word by 12-bit FIFO for data buffering.
The HI-3717 is available in very small 44-pin 7mm x 7mm
Chip-scale (QFN) and 44-pin Quad Flat Pack (PQFP) plastic
packages.
PIN CONFIGURATIONS
(Top View)
-
-
-
-
-
-
-
-
-
-
-
NOCONV
RINB-40
RINB
RINA
RINA-40
GND
TFIFO
TEMPTY
INSYNC
SYNC0
SYNC1
- 1
- 2
- 3
- 4
- 5
- 6
- 7
- 8
- 9
- 10
- 11
44
43
42
41
40
39
38
37
36
35
34
VDD
C1-
C1+
V+
GND
C2+
C2-
V-
TXHA
FEATURES
·
Compliant with ARINC 717 and ARINC 573 standards
·
Operates from a single +3.3V supply with on-chip
converters to provide proper voltages for both Harvard
Bi-Phase (HPB) and Bi-Polar Return-to-Zero (BPRZ)
outputs
HI-3717PCI
HI-3717PCT
HI-3717PCM
33
32
31
30
29
28
27
26
25
24
23
-
-
-
-
-
-
-
-
-
-
-
OUTHA
TXOUTHA
TXOUTHB
OUTHB
TXHB
TXBA
OUTBA
TXOUTBA
TXOUTBB
OUTBB
TXBB
·
One selectable receive channel as HBP or BPRZ with
integrated analog line receiver
·
Both HBP and BPRZ transmitters have integrated line
drivers as well as digital outputs
44 - Pin Plastic 7mm x 7mm
Chip-Scale Package (QFN)
VDD
C1-
C1+
V+
GND
C2+
C2-
V-
TXHA
·
32-word by 12-bit FIFOs for both the receive and the
transmit channel
7.5
μ
s or 10
μ
s
·
Digital transmitter outputs available for use with
external line drivers
44
43
42
41
40
39
38
37
36
35
34
·
Programmable slew rates on transmit channels: 1.5
μ
s,
-
-
-
-
-
-
-
-
-
-
-
MATCH
RFIFO
ROVF
MR
RSEL
GND
SI
SCK
SO
CS
ACLK
-
-
-
-
-
-
-
-
-
-
-
12
13
14
15
16
17
18
19
20
21
22
·
Programmable bit rates: 384, 768, 1536, 3072, 6144,
12288, 24576, 49152 and 98304 bits/sec (32, 64, 128,
256, 512, 1024, 2048, 4096 and 8192 words/sec)
·
Enhanced Sync detection allows multiple false sync
marks in user data while still synchronizing within 8
seconds
·
Fast SPI transmitter write and receiver read modes
·
Match pin flags when preprogrammed word count /
subframe is received
NOCONV
RINB-40
RINB
RINA
RINA-40
GND
TFIFO
TEMPTY
INSYNC
SYNC0
SYNC1
- 1
- 2
- 3
- 4
- 5
- 6
- 7
- 8
- 9
- 10
- 11
HI-3717PQI
HI-3717PQT
HI-3717PQM
33
32
31
30
29
28
27
26
25
24
23
-
-
-
-
-
-
-
-
-
-
-
OUTHA
TXOUTHA
TXOUTHB
OUTHB
TXHB
TXBA
OUTBA
TXOUTBA
TXOUTBB
OUTBB
TXBB
·
Frame / subframe word count indicator
·
Industrial and Extended temperature ranges
·
Burn-in available
44 - Pin Plastic Quad Flat Pack (PQFP)
(DS3717 Rev. B)
HOLT INTEGRATED CIRCUITS
www.holtic.com
MATCH
RFIFO
ROVF
MR
RSEL
GND
SI
SCK
SO
CS
ACLK
-
-
-
-
-
-
-
-
-
-
-
12
13
14
15
16
17
18
19
20
21
22
11/11
HI-3717
BLOCK DIAGRAM
VDD
TXHA
5Ω
OUTHA
TXOUTHA
TXOUTHB
Transmit
32 x 12-BIT
FIFO
Transmit
Rate
Selection
HBP
Encoder
Slew
Rate
&
Loopback
Test
Control
BPRZ
Encoder
Line
Driver
37.5Ω
37.5Ω
5Ω
OUTHB
TXHB
TXBA
5Ω
Line
Driver
37.5Ω
37.5Ω
5Ω
OUTBA
TXOUTBA
TXOUTBB
OUTBB
TXBB
NOCONV
Transmit FIFO
Status Register
TXFSTAT
+3.3V
V+
V+
V-
V-
47uF
MR
SCK
CS
SI
SO
ARINC 717
Clock
Divider
Control
Register 0
CTRL0
Control
Register 1
CTRL1
SPI
Interface
DC / DC
Converter
C1+
C1-
C2+
ACLK
C2-
47uF
0.47uF
2.2uF
RSEL
Receive FIFO
Status Register
RXFSTAT
FIFO Status Pin
Assignment
Register
FSPIN
Word Count
Utility Register
WRDCNT
MATCH
RFIFO
TFIFO
HBP Line
Receiver
RINA
RINB
RINA-40
RINB-40
40 KΩ
40 KΩ
TEMPTY
HBP / BPRZ
Data
Sampler
HBP / BPRZ
Clock
Recovery
&
Decoder
SYNC
Detect
RECEIVE
32 x 12-BIT
FIFO
ROVF
BPRZ Line
Receiver
INSYNC
SYNC1
SYNC0
GND
FIGURE 1.
HOLT INTEGRATED CIRCUITS
2
HI-3717
PIN DESCRIPTIONS
SIGNAL
NOCONV
RINB-40
RINB
RINA
RINA-40
GND
TFIFO
TEMPTY
INSYNC
SYNC0
SYNC1
MATCH
RFIFO
ROVF
MR
RSEL
SI
SCK
SO
CS
ACLK
TXBB
OUTBB
TXOUTBB
TXOUTBA
OUTBA
TXBA
TXHB
OUTHB
TXOUTHB
TXOUTHA
OUTHA
TXHA
V-
C2-
C2+
V+
C1+
C1-
VDD
FUNCTION
INPUT
INPUT
INPUT
INPUT
INPUT
POWER
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
INPUT
INPUT
INPUT
INPUT
OUTPUT
INPUT
INPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
CONVERTER
CONVERTER
CONVERTER
CONVERTER
CONVERTER
CONVERTER
POWER
DESCRIPTION
Disables on-chip DC-DC voltage converter
Alternate receiver negative input. Requires external 40K ohm resistor
Receiver negative input. Direct connection to ARINC 717 bus (BPRZ or HBP)
Receiver positive input. Direct connection to ARINC 717 bus (BPRZ or HBP)
Alternate receiver positive input. Requires external 40K ohm resistor
Chip 0V Supply (All GND pins on package must be connected)
Output is user programmable to indicate the Transmit FIFO Full or Half-full state.
See FSPIN<5>, in Table 7, FIFO Status Pin Assignment Register.
Output goes high when the transmit FIFO is empty
Output goes high when the receiver is synchronized to the incoming data. Synchroni-
zation occurs at the next valid sync mark following the detection of the proper
number and order of consecutively spaced sync marks. See Table 3.
Output in conjunction with SYNC1 output indicates when each of the four ARINC 717
subframe sync words are received. Only valid when the INSYNC pin is high.
Output in conjunction with SYNC0 output indicates when each of the four ARINC 717
subframe sync words are received. Only valid when the INSYNC pin is high.
Output goes high when the value of the Frame Word Count Register matches the
value in the Frame Count Utility Register, WRDCNT.
Output is user programmable to indicate the Receive FIFO Full, Half-full or Empty
state. See FSPIN<7:6> in Table 7, FIFO Status Pin Assignment Register.
Receive FIFO Overflow. Output goes high when an attempt is made to load a full
Receive FIFO
Master Reset, active low
Selects either HBP or BPRZ Receiver. OR’d with RXSEL bit in Control Register 0
SPI interface serial data input
SPI Clock. Data is shifted into SI and out of SO when CS is low.
SPI Interface seral data output
Chip Select. Data is shifted into SI and out of SO using SCK when CS is low
Master timing source for receiver and transmitters. 24 MHZ ±0.1%
Bi-Polar Return-to-Zero (BPRZ) digital low output (external line driver required)
Alternate Bi-Polar Return-to-Zero (BPRZ) Line Driver low output. Requires external
32.5 ohm resistor
Bi-Polar Return-to-Zero (BPRZ) Line Driver low output. Direct connect to ARINC 717
bus
Bi-Polar Return-to-Zero (BPRZ) Line Driver high output. Direct connect to ARINC
717 bus
Alternate Bi-Polar Return-to-Zero (BPRZ) Line Driver high output. Requires external
32.5 ohm resistor
Bi-Polar Return-to-Zero (BPRZ) digital high output (external line driver required)
Harvard Bi-Phase (HBP) digital low output (external line driver required)
Alternate Harvard Bi-Phase (HBP) Line Driver low output. Requires external 32.5
ohm resistor
Harvard Bi-Phase (HBP) Line Driver low output. Direct connect to ARINC 717 bus
Harvard Bi-Phase (HBP) Line Driver high output. Direct connect to ARINC 717 bus
Alternate Harvard Bi-Phase (HBP) Line Driver high output. Requires external 32.5
ohm resistor
Harvard Bi-Phase (HBP) digital high output (external line driver required)
DC/DC converter negative voltage
DC/DC converter fly capacitor for V-
DC/DC converter fly capacitor for V-
DC/DC converter positive voltage
DC/DC converter fly capacitor for V+
DC/DC converter fly capacitor for V+
Chip +3.3V Supply
Internal
Pull-up / Down
50KΩ pull-down
50KΩ pull-up
50KΩ pull-down
50KΩ pull-down
50KΩ pull-down
50KΩ pull-up
50KΩ pull-down
TA B L E 1 .
HOLT INTEGRATED CIRCUITS
3
HI-3717
SERIAL PERIPHERAL
INTERFACE (SPI)
SPI BASICS
The HI-3717 uses an SPI (Serial Peripheral Interface) for host
access to internal registers and data FIFOs. Host serial
communication is enabled through the Chip Select (CS) pin,
and is accessed via a four-wire interface consisting of Serial
Data Input (SI) from the host, Serial Data Output (SO) to the
host and Serial Clock (SCK). All read / write cycles are
completely self-timed.
The SPI protocol specifies master and slave operation; the
HI-3717 operates as an SPI slave.
The SPI protocol defines two parameters, CPOL (clock
polarity) and CPHA (clock phase). The possible CPOL-CPHA
combinations define four possible “SPI Modes”. Without
describing details of the SPI modes, the HI-3717 operates in
Mode 0 where input data for each device (master and slave) is
clocked on the rising edge of SCK, and output data for each
device changes on the falling edge (CPHA = 0, CPOL = 0). The
host SPI logic must be set for Mode 0 for proper
communications with the HI-3717 .
As seen in Figure 2, SPI Mode 0 holds SCK in the low state
when idle. The SPI protocol transfers serial data as 8-bit bytes.
Once CS is asserted, the next 8 rising edges on SCK latch input
data into the master and slave devices, starting with each byte's
most-significant bit. A rising edge on CS terminates the serial
transfer and re-initializes the HI-3717 SPI for the next transfer.
If CS goes high before a full byte is clocked by SCK, the
incomplete byte clocked into the device SI pin is discarded.
In the general case, both master and slave simultaneously
send and receive serial data (full duplex), per Figure 2 below.
However the HI-3717 operates half duplex, maintaining high
impedance on the SO output, except when actually transmitting
serial data. When the HI-3717 is sending data on SO during
read operations, activity on its SI input is ignored. Figure 3 and
Figure 4 show actual behavior for the HI-3717 SO output.
HI-3717 SPI INSTRUCTIONS
Instruction op codes are used to read, write and configure the
HI-3717. Each SPI read or write operation begins with an 8-bit
instruction. When CS goes low, the next 8 clocks at the SCK
pin shift an instruction op code into the decoder, starting with
the first rising edge. The op code is shifted into the SI pin, most
significant bit (MSB) first. The SPI can be clocked up to10 MHz.
The SPI instructions are of a common format. The most
significant bit (MSB) specifies whether the instruction is a write
“0” or read “1” transfer.
R
/W
X
MSB
7
6
X
5
X
4
X
3
X
2
X
1
X
0
LSB
SPI INSTRUCTION FORMAT
For write instructions, the most significant bit of the data word
must immediately follow the instruction op code and is clocked
into its register on the next rising SCK edge. Data word length
varies depending on word type written: 8-bit Control & Status
Register writes, 16-bit Word Count Utility Register writes and
16-bit Transmit FIFO writes.
For read instructions, the most significant bit of the requested
data word appears at the SO pin at the next falling SCK edge
after the last op code bit is clocked into the decoder. As in write
instructions, the data field bit-length varies with read instruction
type.
Since HI-3717 operates in half-duplex mode, the host discards
the dummy byte it receives while serially transmitting the
instruction op code to the HI-3717.
SCK
(SPI Mode 0)
SI
SO
CS
High Z
MSB
MSB
LSB
LSB
High Z
FIGURE 2. Generalized Single-Byte Transfer Using SPI Protocol Mode 0
HOLT INTEGRATED CIRCUITS
4
HI-3717
Figure 3 and Figure 4 show read and write timing as it appears
for a single-byte and dual-byte register operation. The
instruction op code is immediately followed by a data byte
comprising the 8-bit data word read or written. For a register
read or write, CS is negated after the data byte is transferred.
Table 2 summarizes the HI-3717 SPI instruction set.
Note:
SPI Instruction op-codes not shown in Table 2 are
“reserved” and must not be used. Further, these op-codes will
not provide meaningful data in response to a read instruction.
Two instruction bytes cannot be “chained”; CS must be negated
after each instruction, and then reasserted for the following
Read or Write instruction.
0
SCK
MSB
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
LSB
SI
Op-Code Byte
SO
High Z
Data Byte
CS
Host may continue to assert CS
here to read sequential byte(s)
when allowed by the instruction.
Each byte needs 8 SCK clocks.
MSB
LSB MSB
High Z
FIGURE 3. Single-Byte Read From a Register
0
SCK
SPI Mode 0
MSB
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
LSB MSB
LSB MSB
LSB
SI
Op-Code Byte
SO
High Z
Data Byte 0
Data Byte 1
CS
Host may continue to assert CS
here to write sequential byte(s)
when allowed by the SPI instruction.
Each byte needs 8 SCK clocks.
FIGURE 4. 2-Byte SPI Write Example
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