NJW4302
THREE-PHASE DC BRUSHLESS MOTOR CONTROL IC
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GENERAL DESCRIPTION
The NJW4302 is a three-phase DC brushless motor
pre-driver IC for precision applications.
The NJW4302 consists of PWM driver, motor velocity
control, FG(Frequency Generator) output, and voltage
velocity integration circuit.
The NJW4302 realizes stabilized velocity and it is
suitable for printer, FAX, and other DC motor control
systems.
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PACKEGE OUTLINE
NJW4302FG1
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FEATURES
•
Speed discriminator and PLL speed
control circuit
•
Direct PWM driver
•
CR oscillator
•
Lock protection output
•
Break circuit (short circuit braking)
•
Start/stop switch Start/Stop Switch
Circuit
•
Current limit circuit
•
Thermal shut down/Under voltage
lockout circuit
•
FG output amplifier/Integrating circuit
•
Shunt regulator output : 5V
•
Bi-CMOS technology
•
PACKAGE OUTLINE QFP64G1
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PIN CONFIGRATION
sBLOCK
DIAGRAM
NJW4302
sPIN
DESCRIPTION
SYMBOL
H1+,H1-
H2+,H2-
H3+,H3-
UH
VH
WH
UL
VL
WL
V
+
VREG
GND
VSH
PIN No.
50, 51
52, 53
54, 55
58
60
62
57
59
61
2~4
5
6,7
42,43
12
Power-supply voltage pin
Connect a noise decoupling capacitor between these pins and the ground.
Shunt regulator output pin
Ground pins
These pins are all connected internally to the ground(GND).
Shunt regulator ON/OFF output pin
“L”:ON
“H” or open:OFF
CR
13
PWM oscillator frequency setting pin
Three blocks use the oscillator: motor constraint detection circuit, clock disconnection protection circuit
and others
CROCK
R
C
14
15
16
Reference clock signal oscillator pin
Connect a capacitor between this pin to the ground.This oscillator provides clock signal when motor is locked.
VCO oscillation frequency setting pin
Connect a resistor between this pin and the ground.
VCO oscillation frequency setting pin
Connect a resister between this pin and ground.
Set the value of the capacitor so that the oscillator frequency does not exceed 1MHz.
FILI
20
VCO filter amplifier input pin
This pin is connected to VCO PLL output with 10KΩ resistor internally in the IC.
FILO
D OUT
P OUT
LD
19
25
26
27
VCO filter amplifier output pin
This pin is connected to VCO circuit internally in the IC.
Speed discriminator output pin
Output“L”level for over speed.
PLL output pin
Output the phase comparison result for 1/2fCLK and1/2fFG.
Lock detection output pin
Open collector becomes“L”within the speed lock range(±6.25).
INT REF
INT IN
INT OUT
TOC
21
24
23
22
Integrating amplifier forward rotation input(a potential of 1/2V
+
)
Negative input for Integration amplifier
Output for Integration amplifier
Torque command input pin
This pin is normally connected to the INT OUT pin. When the TOC voltage level falls,the UL,VL and Wl PWM
duties are changed to increase.
FG IN+
47
Input pin for FG amplifier forward rotation (a potential of 1/2V
+
)
Connect a noise decoupling capacitor between V
+
terminal and the ground.
Output pins(open collector sink outputs).
Duty control implement with PWM signal.
Output pins(for fixed current source )
DESCRIPTION
Hall input pins
Positive input terminal is defined as IN
+
,Negative input terminal as IN
-
respectably.
Positive input is defined as IN
+
> IN
-
as Negative.
NJW4302
FG IN-
FGO
FGSO
46
45
44
FG amplifier reverse rotation input.
FG amplifier output.
FG amplifier output(after the schmitt)
Open collector output.
RF
56
Output current detection
Connect a resistor between this pin and GND pin.The output limitation maximum current(IOUT)is set to be
0.5/Rf.
S/S
34
Start⋅Stop control
“L”:Start
“H”or Open:Stop
F/R
29
Forward/reverse rotation control
“L”:Forward
“H”or Open:reverse
BR
28
Brake control (short braking operation)
“L”:Start
“H”or Open:Brake
CLK
N1
N2
NC
33
35
36
1,8~11
17,18,30~32
37~41,48,49
63,64
Non Connection
External clock signal input
10kHz max.
Speed discriminator count switching
NJW4302
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FUNCTIONAL DESCRIPTION
1.VCO circuit
The variable range of PLL circuit is determined by two factors: VCO frequency determined by RC value
connected to Pin 15 and Pin 16 and VCO loop filter constants. VCO frequency range must be within 160kH
Z
to
1.0MH
Z.
The typical external value is as follows:
R=20kΩ,C=100pF.
The filter constants are C=0.47µF,R=27kΩ.
2. Output drive circuit
The PWM control is made by upper side of external transistor.
3. Speed lock range
The speed lock range is ±6.25% of fixed speed. When the motor speed is within the lock range, the LD pin
(an open collector output)goes “L”. If the motor speed goes out of the lock range, the LD pin goes “H”.
Please be noted that the LD signal may go on during startup.
4. PWM frequency
The PWM frequency is determined by resistor and capacitor value connected to the CR pin.
The PWM frequency can be expressed as:
fPWM=1/(0.48CR)
When C=1500pF,R=75KΩ,the PWM frequency goes about 19KHz.
5. Lock detection circuit(CLOCK)
Lock detection circuit protects the driver IC and the motor from fatal over current failure when the motor is
locked during startup. If the LD output remains “H” (motor lock state) for a certain period (Hold time),all phase of
upper side transistors are to be turned off.
The hold time can be programmed by capacitor value attached to the CLOCK pin by the following:
Set time(sec) =66×C(µF)
With C=0.068µF,the hold time can be programmed for approximately 4.5 sec.
Once Lock detection circuit is activated, the state remains unchanged unless it is turned off, or stopped.
This function can be disabled when the CLOCK pin is connected to the ground.
6. Forward / Reverse(F/R)Switching
The direction control can be made with the state of the F/R pin. The direction can be changed even during the
motor in motion.
7. Blake Switch
NJW4302 uses a short brake method that turns on all phase of upper side transistors for braking. During the
time, all lower side transistors are turned off.
8.
VREG pin/VSH pin
NJW4302 includes a regulator to generate for +5V regulated IC supply when the motor drive circuit
is designed with a single power supply. The VREG pin and V+ pin compose a shunt regulator for 5V±5%
output with a external resistor and a transistor. To use the regulator, the VSH pin must be either “H”, or
Open. Otherwise, the VSH pin must be “L” and the VREG pin is to be opened.
NJW4302
9. Frequency Generator (FG) Amplifier
The internal FG amplifier with few passive components composes a filter amplifier shown in the
application. Circuit for noise rejection. The output voltage of the amplifier must be at least 250mA p-p since
it feature Schmitt comparator.
The capacitor connected between the FGIN+ pin and the ground is necessary for bias voltage
stabilization and initial reset pulse generation for the internal logic. The reset pulse is generated when the
FGIN+ pin goes from 0 to about 1.25V.
10. Integrating Amplifier
The integrating amplifier integrates the D-out and P-out and converts them to speed command voltage.
During the time, it also sets the control loop gain and frequency characteristics using external
components.
11. Speed Control Circuit
NJW4302 features two speed control method; speed discriminator
circuit with PLL circuit and phase
comparison circuit. The FG pulse frequency is controlled to be the same frequency with a clock frequency input
to the CLK pin. Therefore, the motor speed can be controlled by changing the clock frequency.
The motor speed (N) can be expressed as:
N=CLK (Hz)×(60/FGP)[RPM] ( FGP: Number of FG pulse per one rotation)
Given that the oscillation frequency range is 160kHz~1.0MH
Z
and the number of counts is 1024,the range of
clock frequency is 156H
Z
~960H
Z ,
and therefore the motor speed can be changed from 260rpm
to 1600rpm.
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