Ordering number : ENA1780
LC87F83C8A/AU
LC87F8396A/AU
LC87F8364A/AU
Overview
CMOS IC
FROM 128K byte, RAM 6K byte on-chip
8-bit ETR Microcontroller
The LC87F83C8A/AU/96A/AU/64A/AU is an 8-bit ETR microcomputer that, centered around a CPU running at a
minimum bus cycle time of 74.04 ns, integrate on a single chip a number of hardware features such as 128K-bytes of
flash ROM maximum (onboard rewritable), 6K-bytes of RAM maximum, Onchip debugging, direct control of
necessary CD mechanism and CD-DSP for car audio, in the radio reception, the on-chip high-performance PLL circuit
provides a high-speed Lock-Up circuit to search for alternative frequency of RDS in a short time, the ability to control
the C/N characteristics of a local oscillator, and the high S/N through the direct PLL configuration, two sophisticated
16-bit timers/counters (may be divided into 8-bit timers), four 8-bit timers with a prescaler, a base timer serving as a
time-of-day clock, two synchronous SIO ports (with automatic block transmission/reception capabilities), an
asynchronous/synchronous SIO port, two UART ports (full duplex), four 12-bit PWM channels, an 8-bit 10-channel
AD converter, a high-speed clock counter, a system clock frequency divider, and a 29-source 10-vector interrupt
feature.
ROM for each model/Table RAM capacity
Type No.
LC87F8364A/AU
LC87F8396A/AU
LC87F83C8A/AU
Flash ROM (byte)
64K
96K
128K
RAM (byte)
4K
6K
6K
Features
■
Flash ROM
•
Single 5V power supply, on-board writeable
•
Block erase in 128 byte units
* This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by
SANYO Semiconductor Co., Ltd.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer
'
s products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer
'
s products or
equipment.
Ver.1.03
20211HKPC 20100603-S00007, S00009, S00010, S00012, S00013, S00014 No.A1780-1/31
LC87F83C8A/C8AU/96A/96AU/64A/64AU
■
Minimum Bus Cycle Time
•
74.04ns (13.5MHz)
Note: Bus cycle time indicates the speed to read ROM.
■
Minimum Instruction Cycle Time (tCYC)
•
222ns (13.5MHz)
■
Ports
•
Normal withstand voltage I/O ports
Ports whose I/O direction can be designated in 1 bit units: 57 (P1n, P2n, P30 to P35, P70 to P73, P8n, PBn, PCn,
SI2Pm, PWM0, PWM1, XT2, n=0 to 7, m=0 to 3)
Ports whose I/O direction can be designated in 2 bit units: 16 (PEn, PFn n=0 to 7)
Ports whose I/O direction can be designated in 4 bit units: 8 (P0n n=0 to 7)
•
Normal withstand voltage input ports:
1 (XT1)
•
Main charge pump output ports:
1 (EO)
•
Sub charge pump output ports:
1 (SUBPD)
•
AM local oscillator input ports:
1 (AMIN)
•
FM local oscillator input ports:
1 (FMIN)
•
High-speed, universal counter input ports:
1 (HCTR)
•
Universal counter input ports:
1 (LCTR)
•
Internal low voltage output ports:
1 (VREG)
•
Dedicated oscillator ports:
2 (CF1, CF2)
•
Reset pin:
1 (RES)
•
Digital power pins:
6 (VSSn, VDDn n=1, 2, 4)
•
Analogue power pins:
2 (AVSSn, AVDD)
■
Timers
•
Timer 0: 16-bit programmable timer/counter with capture register
Mode 0: 8-bit programmable timer with an 8-bit programmable prescaler (with two 8-bit capture registers)
×
2 channels
Mode 1: 8-bit programmable timer with an 8-bit programmable prescaler (with two 8-bit capture registers)
+ 8-bit programmable counter (with two 8-bit capture registers)
Mode 2: 16-bit programmable timer with an 8-bit programmable prescaler
(with two 16-bit capture registers)
Mode 3: 16-bit programmable counter (with 2 16-bit capture registers)
•
Timer 1: 16-bit programmable timer/counter that support PWM/ toggle output
Mode 0: 8-bit programmable timer with an 8-bit prescaler (with toggle outputs)
+ 8-bit programmable timer/counter (with toggle outputs)
Mode 1: 8-bit PWM with an 8-bit prescaler
×
2 channels
Mode 2: 16-bit programmable timer/counter with an 8-bit prescaler (with toggle outputs)
(toggle outputs also from the lower-order 8 bits)
Mode 3: 16-bit programmable timer with an 8-bit prescaler (with toggle outputs)
(The lower-order 8 bits can be used as PWM.)
•
Timer 4: 8-bit programmable timer with a 6-bit prescaler
•
Timer 5: 8-bit programmable timer with a 6-bit prescaler
•
Timer 6: 8-bit programmable timer with a 6-bit prescaler (with toggle outputs)
•
Timer 7: 8-bit programmable timer with a 6-bit prescaler (with toggle outputs)
•
Base timer
1) The clock is selectable from the subclock (32.768kHz crystal oscillator), cycle clock (tCYC), and timer 0
prescaler output.
2) Interrupts programmable in 5 different time schemes.
■
High Speed Clock Counter
1) Can count clocks with a maximum clock rate of 20MHz (When High-speed clock counter is used, timer 0
cannot be used).
2) Can generate output real time.
No.A1780-2/31
LC87F83C8A/C8AU/96A/96AU/64A/64AU
■
SIO: 3 channels
•
SIO 0: 8 bit synchronous serial interface
1) LSB first/MSB first mode selectable
2) Built-in 8-bit baudrate generator (4/3 to 512/3 tCYC transfer clock cycle)
3) Automatic continuous data transmission (1 to 256 bits)
•
SIO 1: 8 bit asynchronous/synchronous serial interface
Mode 0: Synchronous 8-bit serial I/O (2 to or 3 to wire configuration, 2 to 512 tCYC transfer clocks)
Mode 1: Asynchronous serial I/O (Half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates)
Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks)
Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect)
•
SIO2: 8 bit synchronous serial interface
1) LSB first mode
2) Built-in 3-bit baudrate generator (4/3 to 512/3 tCYC transfer clock cycle)
3) Automatic continuous data transmission (1 to 32 bytes)
■
UART: 2 channels
1) Full duplex
2) 7/8/9 bit data bits selectable
3) 1 stop bit (2 bits in continuous transmission mode)
4) Built-in 8-bit baudrate generator (with baudrates of 16/3 to 8192/3 tCYC)
■
AD Converter: 8 bits
×
10 channels
■
PWM: Multifrequency 12-bit PWM
×
4 channels
■
Remote Control Receiver Noise Filtering Function (sharing pins with P73, INT3, and T0IN)
1) Noise filter time constant selectable from 1 tCYC, 32 tCYC, and 128 tCYC
2) The noise filtering function is available for the INT3, T0IN, or T0HCP signal at P73. When P73 is read with an
instruction, the signal level at that pin is read regardless of the availability of the noise filtering function.
■
Watchdog Timer
■
Interrupts
•
External RC watchdog timer
•
Interrupt and reset signals selectable
•
29 sources, 10 vector addresses
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of
the level equal to or lower than the current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level
takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector
address takes precedence.
No.
1
2
3
4
5
6
7
8
9
10
Vector Address
00003H
0000BH
00013H
0001BH
00023H
0002BH
00033H
0003BH
00043H
0004BH
Level
X or L
X or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
INT0
INT1
INT2/T0L/INT4
INT3/INT5/Base timer (BT0, 1)
T0H/INT6
T1L/T1H/INT7
SIO0/UART1 receive/UART2 receive
SIO1/SIO2/UART1 transmit/UART2 transmit
ADC/T6/T7/PWM4, PWM5
Port 0/T4/T5/PWM0, PWM1
Interrupt Source
•
Priority levels X
>
H
>
L
•
Of interrupts of the same level, the one with the smallest vector address takes precedence.
•
The Base timers are two interrupt sources of BT0 and BT1, it is one interrupt source by PWM0 and 1, it is one
interrupt source by PWM4 and 5.
No.A1780-3/31
LC87F83C8A/C8AU/96A/96AU/64A/64AU
■
Subroutine Stack Levels
•
16 bits
×
8 bits
•
24 bits
×
16 bits
•
16 bits
÷
8 bits
•
24 bits
÷
16 bits
•
3072 levels maximum (1/2 of capacity of RAM, the stack is allocated in RAM.)
■
High-speed Multiplication/Division Instructions
(5 tCYC execution time)
(12 tCYC execution time)
(8 tCYC execution time)
(12 tCYC execution time)
■
Oscillation Circuits and PLL
•
RC oscillator circuit (internal):
•
Main XT crystal oscillator circuit:
•
Sub XT crystal oscillator circuit:
For system clock
For system clock with internal Rf, Rd
For time-of-day clock, for low-speed system clock with internal Rf
and external Rd
•
Multifrequency RC oscillator circuit (internal): For system clock
•
PLL circuit (internal):
For AM/FM tuner
■
System Clock Divider Function
•
Can run on low current.
•
The minimum instruction cycle selectable from 222ns, 444ns, 888ns, 1.78μs, 3.55μs, 7.10μs, 14.2μs, 28.4μs,
and 56.8μs.
■
PLL Block
•
Twelve reference frequencies when main XT is 13.5MHz: 1kHz, 3kHz, 3.125kHz, 5kHz, 6.25kHz, 9kHz, 10kHz,
12.5kHz, 25kHz, 30kHz, 50kHz, and 100kHz
•
Range of input frequency
1) AMIN: 0.5 to 40MHz
2) FMIN: 10 to 150MHz
3) HCTR: 0.4 to 12MHz
4) LCTR: 100 to 500kHz
•
Supports dead zone control.
•
Built-in unlock detection circuit.
•
This 20-bit counter can be used for frequency measurement.
■
Universal Counter
■
Standby Function
•
HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
1) Oscillation is not halted automatically.
2) Canceled by system reset, detection VDET0 or occurrence of interrupt.
•
HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
1) The main XT crystal oscillators, RC, and sub XT crystal oscillators automatically stop operation.
2) There are four ways of resetting the HOLD mode.
(1) Setting the Reset pin to the lower level.
(2) Voltage descent detection (VDET1)
(3) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level.
(4) Having an interrupt source established at port 0.
•
X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer.
1) The main XT crystal oscillators, and RC oscillators automatically stop operation.
2) The state of crystal oscillation established when the HOLD mode is entered is retained.
3) There are five ways of resetting the X'tal HOLD mode.
(1) Setting the Reset pin to the low level.
(2) Voltage descent detection (VDET0)
(3) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level.
(4) Having an interrupt source established at port 0.
(5) Having an interrupt source established in the base timer circuit.
No.A1780-4/31
LC87F83C8A/C8AU/96A/96AU/64A/64AU
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Reset
•
External reset
•
Voltage descent detection (VDET0, VDET1) reset circuit (internal)
•
Permits software debugging with the test device installed on the target board.
•
QIP100E (Lead Free Product)
•
LC87F83C8A/96A/64A
•
LC87F83C8AU/96AU/64AU (User writing)
■
Onchip Debugging Function
■
Shipping Form
■
Flash ROM Version
No.A1780-5/31
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