Absolute single-turn hollow shaft encoders
BOSH –
Dignalizer
SSI
features
• high resolution single-turn encoders 18 bit
• SSI interface programmable
• permanent self-test
• reference point programmable
• end hollow shaft
version
5 VDC
version
10 - 30 VDC
general data
voltage supply
supply current
no load
output circuit
max. resolution
max. clock frequency
repeatability
direction of rotation
5 VDC ±5% (05C)
10 - 30 VDC (24C)
typ. 120 mA (at 5VDC) (05C)
typ. 50 mA (at 24 VDC) (24C)
SSI, complementary RS 422,
binary- and Gray code
18 Bit (1 step = 5‘‘)
1,1 MHz
0,012°
looking at the flange, position
counts up as the shaft rotates
clockwise (CW), programmable
mechanical data
max. revolutions
moment of inertia
torque
product life
max. protection class
material
weight
mech. 6‘000 rpm
electr. 6‘000 rpm
typ. 18,4 x 10
-7
kgm
2
typ. 1,75 cNm
(3‘000 rpm 20 °C/ IP 42)
depending on ambient conditions
(typ. 10
9
revolutions)
IP 65
housing: aluminum
approx. 300 g
ambient conditions
temperature range
relative humidity
vibration
(sine)
vibration
(random)
shock
-20...+85 °C
max. 95%
non condensing
IEC 60068-2-6
(≤ 100 m/s
2
/ 10 - 2‘000 Hz)
150 min per axis
IEC 60068-2-64
(≤ 0,1 g
2
/Hz / 20 - 1‘000 Hz)
30 min per axis
IEC 60068-2-27
(≤ 500 m/s
2
, 11 ms)
10 pulses per axis and direction
EN 61000-6-2
EN 61000-6-3
noise immunity
emitted interference
2. 54
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Absolute single-turn hollow shaft encoders
BOSH –
Dignalizer
SSI
commands to encoder and setting of parameters
Multibyte commands* and parameters can be sent by asyn-
chronous protocol with parameterized baud rate.
The multibyte protocol consists of length byte, address byte,
command byte, data bytes and LRC byte.
read out of position values
The SSI interface can be used especially for real time signal
processing. It is possible to precisely scan the angle informa-
tion with the first negative clock.
T* (single-turn bits)
t
1
SSICLOCK
T
t
3
length
slave
address
command
(memory address),
(data)
checksum
LRC
SSIDATA
t
2
The 8 data bits have are embeded between a start bit (LOW)
and a stop bit (HIGH).
start bit
8 data bits,
no parity bit
stop bit
n
MSB
n-1
1
0
LSB
single-turn MSB
single-turn LSB
Important: The SSI protocol does not start with zeros. NSSICLOCK
and NSSIDATA are not symbolized.
T = 0,9 to 14 µs
0,45 µs <t1 <t3
t2
≥
0,6 µs
t3 = 2, 5, 10 or 20 µs
SSICLOCK
LSB
MSB
NSSICLOCK
T=1s/19200
The monoflop-time (t3) is programmable (Default 20 µs).
Please keep the condition t3
≥
1,4 *T.
Setting of parameters
It is always possible to set parameter over the SSI interface,
even if the encoder is in operation.
For example:
- SSI bit format (position resolution)
- direction of rotation CW/CCW
- monoflop time
- interface mode
- compensation of propagation time
- baud rate for parameter setting and programming
- signal code (binary, Gray)
Additional features:
- efficient error handling
- memory for operating time
- incremental totalisator (number of rotations)
- preset function
The response on commands (data/„acknowledge“/„negative
acknowledge“) has to be read out at the SSI interface before
reading the next position value.
Reading out of position values and programmable of
Dignalizer
is also possible via PCI-board.
See chapter accessories.
* With endshaft mounting, commands and parameter setting
by singlebyte protocol. Description on request.
inputs and outputs
Control signals to V/R* and ZERO
Level HIGH > 0,8 * +Vs
Level LOW < 0,2 * +Vs
Connection V/R*-input with 15 kOhms against+Vs,
ZERO-input with 15 kOhms against 0 V
(3 kOhms for version
05C).
Output signal from DV*
Connection DV*-output push-pull max. 30 mA
(with 10 kOhms against +Vs for version
05C)
I/O description
V/R*
Input to set direction of rotation. Input is normally HIGH.
V/R*-HIGH corresponds to increasing position values
while looking at flange and shaft rotation in clockwise
direction (CW). V/R*-LOW corresponds to increasing
position values while looking at flange and shaft rotation
in counter- clockwise direction (CCW). Read-in of V/R*
voltage occurs during encoder power-on.
ZERO Input to set position to zero. Input is normally LOW.
Zero setting procedure is initiated by a HIGH-pulse
(pulse length
≥
100 ms). For maximum disturbance
immunity, connect input to 0 V.
DV*
Output for error (data valid). Output is LOW-active, it
indicates an error with LOW-voltage.
2. 56
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FPGA/CPLD
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