844H90VTE-SY datasheet, PDF - EEWORLD Datasheet

844H90VTE-SY: DescriptionBase Station/Broadcast Transmission Antenna, 870MHz Min, 960MHz Max, 13.1dB Gain, 90deg 3dB Beamwidth; CategoryWireless rf/communication Radio frequency and microwave; File Size236KB，1 Pages; ManufacturerCommScope Inc

Download Datasheet Parametric View All

844H90VTE-SY Overview

Base Station/Broadcast Transmission Antenna, 870MHz Min, 960MHz Max, 13.1dB Gain, 90deg 3dB Beamwidth

Parameter Name	Attribute value
Maker	CommScope Inc
Reach Compliance Code	unknown
application	CELLULAR/PAGING/TRUNKING FIXED
Beam Width-E	15 deg
Beamwidth-H	90 deg
front to back ratio	40 dB
Gain	13.1 dB
Omnidirectional	YES
Maximum operating frequency	960 MHz
Minimum operating frequency	870 MHz
polarization	LINEAR VERTICAL
RF/Microwave Device Types	BASE STATION/BROADCAST TRANSMISSION ANTENNA
Maximum transmission power	500 W
Maximum voltage standing wave ratio	1.5
Commentary	125 mph

Using I2C with Beaglebone Black: [align=left]Post source: [url=http://blog.csdn.net/wyt2013/article/details/16874823]http://blog.csdn.net/wyt2013/article/details/16874823[/url][/align][align=left]In this article, I will use BBB's I2C...; 刘东丽 DSP and ARM Processors

[NUCLEO-L452RE evaluation] Using Victory 4-digit and a half meter to measure the low power consumption current of STM32L452: [i=s] This post was last edited by zhjb1 on 2017-6-17 15:40 [/i] After some research on the application project, the best multimeter on hand is the Victory 4.5-digit 86E meter with automatic recording...; zhjb1 stm32/stm8

Verilog HDL simulation reports this error, what is the reason: Use modelsim to simulate a simple Verilog program: module 2_n and (in1,in2,out); input in1,in2；output out; assign out=~(in1&in2); endmodule When compiling, an error message appears: near "module": syn...; eeleader-mcu FPGA/CPLD

Spend the Spring Festival and recognize the prawns here: rt...; withoutpoem Embedded System

Ask a question about UCOS interrupt task: Suppose a task is interrupted during execution, and then after saving the scene and entering the interruption, a higher priority task is found. At this time, the higher priority task is executed. When...; jlinkv8 Real-time operating system RTOS

Using Verilog to implement an SDRAM controller based on FPGA: Use Verilog to implement an FPGA-based SDRAM controller....; fanfanme FPGA/CPLD

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ