Preliminary
FM31T372/374/376/378
System Supervisor & Temperature Compensated RTC
(TCXO) with Embedded Crystal
Features
High Integration Device Replaces Multiple Parts
Real-time Clock (RTC)
o
Embedded 32.768kHz Crystal
o
Temperature Compensated
32.768 kHz Clock Output
Low-V
DD
Detection Drives Reset
Watchdog Timer
Early Power-Fail Warning/NMI
Two 16-bit Event Counters with Event Driven
Interrupt Output
Serial Number with Write-lock for Security
Ferroelectric Nonvolatile RAM
4Kb, 16Kb, 64Kb, and 256Kb versions
Unlimited Read/Write Endurance
10 year Data Retention
NoDelay™ Writes
Real-time Clock/Calendar
Temp-Compensated Using On-Chip Sensor
o
5 ppm over -40°C to +85°C
o
Accuracy
2 ½ min. per year
Backup Current 1.4
A
(max.) at +25C
Seconds through Centuries in BCD format
Tracks Leap Years through 2099
No External Crystal Required
Offset Register to Correct for Crystal Aging
Supports Battery or Capacitor Backup
Processor Companion
32.768 kHz Clock Output
Active-low Reset Output for V
DD
and Watchdog
Programmable V
DD
Reset Trip Point
Manual Reset Filtered and Debounced
Programmable Watchdog Timer
Dual Battery-backed Event Counter Tracks
System Intrusions or other Events
Event Counter Driven Interrupt Output
Comparator for Early Power-Fail Interrupt
64-bit Programmable Serial Number with Lock
Fast Two-wire Serial Interface
Up to 1 MHz Maximum Bus Frequency
Supports Legacy Timing for 100 kHz & 400 kHz
Device Select Pins for up to 4 Memory Devices
RTC, Supervisor Controlled via 2-wire Interface
Easy to Use Configurations
Operates from 2.7 to 5.5V
Small Footprint 14-pin “Green” SOIC (-G)
Low Operating Current
-40C to +85C Operation
Description
The FM31T37x is a family of integrated devices that
includes the most commonly needed functions for
processor-based systems. Major features include
nonvolatile F-RAM memory available in various
sizes, temperature-compensated real-time clock with
embedded crystal, 32.768kHz clock output,
low-VDD reset, watchdog timer, battery backed
event counter, event driven interrupt output, lockable
64-bit serial number area, general purpose
comparator that can be used for an early power-fail
(NMI) interrupt or other purpose, and 2-wire serial
interface to a host microcontroller. The family
operates from 2.7 to 5.5V.
The real-time clock (RTC) provides time and date
information in BCD format. It can be permanently
powered from external backup voltage source, either
a battery or a capacitor. The timekeeper uses an
internal 32.768 kHz crystal which is factory-
calibrated for excellent timekeeping accuracy over
the industrial temperature range.
This is a product that has fixed target specifications but are subject
to change pending characterization results.
Rev. 1.1
Apr. 2011
The FM31T37x devices integrate 4Kb, 16Kb, 64Kb,
and 256Kb of F-RAM memory. F-RAM offers
superior write speed and unlimited endurance. This
allows the memory to provide system data collection
and as read/write RAM storage. This memory is truly
nonvolatile rather than battery-backed.
The processor companion includes commonly needed
CPU support functions. Supervisory functions
include a reset output signal controlled by either a
low VDD condition or a watchdog timeout. /RST
goes active when VDD drops below a programmable
threshold and remains active for 100 ms after VDD
rises above the trip point. A programmable watchdog
timer runs from 100 ms to 3 seconds. The watchdog
timer is optional, but if enabled it will assert the reset
signal for 100 ms if not restarted by the host before
the timeout. A flag-bit indicates the source of the
reset.
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
http://www.ramtron.com
Page 1 of 26
FM31T372/374/376/378-G
A general-purpose comparator compares an external
input pin to the onboard 1.2V reference. This is
useful for generating a power-fail interrupt (NMI) but
can be used for any purpose. The family also includes
a programmable 64-bit serial number that can be
locked making it unalterable. Additionally it offers a
dual battery-backed event counter that tracks the
number of rising or falling edges detected on
dedicated input pins.
Pin Configuration
CNT1
CNT2
A0
A1
CAL/PFO
RST
VSS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
Pin Name
CNT1, CNT2
A0, A1
CAL/PFO
VDD
SCL
SDA
F
OUT
/INT
PFI
VBAK
/RST
VSS
VBAK
PFI
/INT
FOUT
SDA
SCL
VDD
Function
Event Counter Inputs
Device Select inputs
Clock Calibration and Early
Power-Fail Output
Reset Input/Output
Ground
Battery-Backup Supply
Early Power-fail Input
Event Counter Driven Interrupt
Output
32.768 kHz Clock Output
Serial Data
Serial Clock
Supply Voltage
Ordering Information
Base Configuration
FM31T378
FM31T376
FM31T374
FM31T372
Memory Size
256Kb
64Kb
16Kb
4Kb
Operating Voltage
2.7-5.5V
2.7-5.5V
2.7-5.5V
2.7-5.5V
Reset Threshold
2.6V, 2.9, 3.9, 4.4V
2.6V, 2.9, 3.9, 4.4V
2.6V, 2.9, 3.9, 4.4V
2.6V, 2.9, 3.9, 4.4V
Ordering Part Number
FM31T378-G
FM31T376-G
FM31T374-G
FM31T372-G
Rev. 1.1
Apr. 2011
Page 2 of 26
FM31T372/374/376/378-G
A1, A0
SCL
SDA
2-Wire
Interface
LockOut
F-RAM
Array
LockOut
RST
Watchdog
LV Detect
Special
Function
Registers
S/N
RTC Registers
FOUT
PFI
+
CAL/PFO
-
~2.4V
1.2V
Temp
Sensor
512Hz
Temperature
Compensated
RTC
Event
Counters
32.768
kHz
/INT
CNT1
CNT2
-
+
VDD
Switched Power
VBAK
Nonvolatile
Battery Backed
Figure 1.
Pin Descriptions
Pin Name
A0, A1
Block Diagram
Type
Input
Pin Description
Device select inputs are used to address multiple memories on a serial bus. To select the device
the address value on the two pins must match the corresponding bits contained in the device
address. The device select pins are pulled down internally.
Event Counter Inputs: These battery-backed inputs increment counters when an edge is detected
on the corresponding CNT pin. The polarity is programmable. These pins should not be left
floating. Tie to ground if pins are not used.
Event Counter Driven Interrupt Output. This is a battery backed open-drain output. It goes low
for at least 100 ms upon changes on either CNT1 or CNT2 pin. This pin can be left floating if
not used.
In normal operation, this is the early power-fail output. In CAL mode, it supplies a 512 Hz
square-wave output for clock calibration.
32.768kHz Clock Output. This is a battery backed open-drain output. This pin can be disabled
by setting the FOEN bit to “0”. This pin can be left floating if not used.
Active low reset output with weak pull-up. Also input for manual reset.
Serial Data & Address: This is a bi-directional line for the two-wire interface. It is open-drain
and is intended to be wire-OR‟d with other devices on the two-wire bus. The input buffer
incorporates a Schmitt trigger for noise immunity and the output driver includes slope control
for falling edges. A pull-up resistor is required.
Serial Clock: The serial clock line for the two-wire interface. Data is clocked out of the device
on the falling edge, and into the device on the rising edge. The SCL input also incorporates a
Schmitt trigger input for noise immunity.
Early Power-fail Input: Typically connected to an unregulated power supply to detect an early
power failure. This pin should not be left floating.
Backup supply voltage: A 3V battery or a large value capacitor. If no backup supply is used, this
pin should be tied to V
DD
.
Supply Voltage
CNT1, CNT2
Input
/INT
Output
CAL/PFO
FOUT
/RST
SDA
Output
Output
I/O
I/O
SCL
Input
PFI
VBAK
VDD
Input
Supply
Supply
Rev. 1.1
Apr. 2011
Page 3 of 26
FM31T372/374/376/378-G
Overview
The FM31T37x family combines a serial nonvolatile
F-RAM, a temperature compensated real-time clock
with embedded crystal, and a processor companion.
The companion is a highly integrated peripheral
including a processor supervisor, a comparator used
for early power-fail warning, nonvolatile event
counters, and a 64-bit serial number. The FM31T37x
integrates these complementary but distinct functions
that share a common interface in a single package.
Although monolithic, the product is organized as two
logical devices, the F-RAM memory, and the
RTC/companion. From the system perspective they
appear to be two separate devices with unique IDs on
the serial bus.
The memory is organized as a stand-alone 2-wire
nonvolatile memory with a standard device ID value.
The real-time clock and supervisor functions are
accessed with a separate 2-wire device ID. This
allows clock/calendar data to be read while
maintaining the most recently used memory address.
The clock and supervisor functions are controlled by
21 special function registers. The RTC and event
counter circuits are maintained by the power source
on the VBAK pin, allowing them to operate from
battery or backup capacitor power when V
DD
drops
below an internally set threshold. Each functional
block is described below.
protected addresses. The special function registers
containing these bits are described in detail below.
Write protect addresses
None
Bottom ¼
Bottom ½
Full array
WP1
0
0
1
1
WP0
0
1
0
1
Processor Companion
In addition to nonvolatile RAM, the FM31T37x
family incorporates a highly integrated processor
companion. It includes a low voltage reset, a
programmable watchdog timer, battery-backed event
counters with interrupt output, a comparator for early
power-fail detection or other purposes, and a 64-bit
serial number.
Memory Operation
The FM31T37x is a family of products available in
different memory sizes including 4Kb, 16Kb, 64Kb,
and 256Kb. The family is software compatible, all
versions use consistent two-byte addressing for the
memory device. This makes the lowest density
device different from its stand-alone memory
counterparts but makes them compatible within the
entire family.
Memory is organized in bytes, for example the 4Kb
memory is 512 x 8 and the 256Kb memory is 32,768
x 8. The memory is based on F-RAM technology.
Therefore it can be treated as RAM and is read or
written at the speed of the two-wire bus with no
delays for write operations. It also offers effectively
unlimited write endurance unlike other nonvolatile
memory technologies. The 2-wire interface protocol
is described further on page 13.
The memory array can be write-protected by
software. Two bits in the processor companion area
(WP0, WP1 in register 0Bh) control the protection
setting as shown in the following table. Based on the
setting, the protected addresses cannot be written and
the 2-wire interface will not acknowledge any data to
Processor Supervisor
Supervisors provide a host processor two basic
functions: detection of power supply fault conditions
and a watchdog timer to escape a software lockup
condition. All FM31T37x devices have a reset pin
(/RST) to drive the processor reset input during
power faults (and power-up) and software lockups. It
is an open-drain output with a weak internal pull-up
to V
DD
. This allows other reset sources to be
wire-OR‟d to the /RST pin. When V
DD
is above the
programmed trip point, /RST output is pulled weakly
to V
DD
. If V
DD
drops below the reset trip point
voltage level (V
TP
) the /RST pin will be driven low. It
will remain low until V
DD
falls too low for circuit
operation which is the V
RST
level. When V
DD
rises
again above V
TP
, /RST will continue to drive low for
at least 100 ms (t
RPU
) to ensure a robust system reset
at a reliable V
DD
level. After t
RPU
has been met, the
/RST pin will return to the weak high state. While
/RST is asserted, serial bus activity is locked out even
if a transaction occurred as V
DD
dropped below V
TP
.
A memory operation started while V
DD
is above V
TP
will be completed internally.
Figure 2 below illustrates the reset operation in
response to the V
DD
voltage.
VDD
VTP
t
RPU
RST
Figure 2. Low Voltage Reset
Rev. 1.1
Apr. 2011
Page 4 of 25
FM31T372/374/376/378-G
The bits VTP1 and VTP0 control the trip point of the
low voltage detect circuit. They are located in register
0Bh, bits 1 and 0.
V
TP
2.6V
2.9V
3.9V
4.4V
VTP1
0 0
0 1
1 0
1 1
VTP0
Watchdog
timeout
WDE
WR3-0 = 1010b to restart
Counter
/RST
100 ms
clock
Timebase
Figure 3. Watchdog Timer
Manual Reset
The /RST pin is bi-directional and allows the
FM31T37x to filter and de-bounce a manual reset
switch. The /RST input detects an external low
condition and responds by driving the /RST signal
low for 100 ms. A manual reset does not set any
flags.
MCU
RST
FM31T37x
The watchdog timer can also be used to assert the
reset signal (/RST). The watchdog is a free running
programmable timer. The period can be software
programmed from 100 ms to 3 seconds in 100 ms
increments via a 5-bit nonvolatile register. All
programmed settings are minimum values and vary
with temperature according to the operating
specifications. The watchdog has two additional
controls associated with its operation, a watchdog
enable bit (WDE) and timer restart bits (WR). Both
the enable bit must be set and the watchdog must
timeout in order to drive /RST active. If a reset event
occurs, the timer will automatically restart on the
rising edge of the reset pulse. If WDE=0, the
watchdog timer runs but a watchdog fault will not
cause /RST to be asserted low. The WTR flag will be
set, indicating a watchdog fault. This setting is useful
during software development and the developer does
not want /RST to drive. Note that setting the
maximum timeout setting (11111b) disables the
counter to save power. The second control is a nibble
that restarts the timer preventing a reset. The timer
should be restarted after changing the timeout value.
The watchdog timeout value is located in register
0Ah, bits 4-0, and the watchdog enable is bit 7. The
watchdog is restarted by writing the pattern 1010b to
the lower nibble of register 09h. Writing this pattern
will also cause the timer to load new timeout values.
Writing other patterns to this address will not affect
its operation. Note the watchdog timer is
free-running. Prior to enabling it, users should restart
the timer as described above. This assures that the
full timeout period will be set immediately after
enabling. The watchdog is disabled when V
DD
is
below V
TP
. The following table summarizes the
watchdog bits. A block diagram follows.
Watchdog timeout
Watchdog enable
Watchdog restart
WDT4-0 0Ah, bits 4-0
WDE 0Ah, bit 7
WR3-0
09h, bits 3-0
Reset
Switch
Switch
Behavior
RST
FM31T37x
drives
100 ms (min.)
Figure 4. Manual Reset
Note that an internal weak pull-up on /RST
eliminates the need for additional external
components.
Reset Flags
In case of a reset condition, a flag will be set to
indicate the source of the reset. A low V
DD
reset is
indicated by the POR flag, register 09h bit 6. A
watchdog reset is indicated by the WTR flag, register
09h bit 7. Note that the flags are internally set in
response to reset sources, but they must be cleared by
the user. When the register is read, it is possible that
both flags are set if both have occurred since the user
last cleared them.
Early Power Fail Comparator
An early power fail warning can be provided to the
processor well before V
DD
drops out of spec. The
comparator is used to create a power fail interrupt
(NMI). This can be accomplished by connecting the
PFI pin to the unregulated power supply via a resistor
divider. An application circuit is shown below.
Rev. 1.1
Apr. 2011
Page 5 of 26
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