CA91C078A-40CG datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > The embedded processor and controller> Microcontrollers and processors> CA91C078A-40CG

CA91C078A-40CG: DescriptionVME Bus Controller, CMOS, CPGA299, CERAMIC, PGA-299; CategoryThe embedded processor and controller Microcontrollers and processors; File Size3MB，350 Pages; ManufacturerSilicon360

Download Datasheet Parametric Compare View All

CA91C078A-40CG Overview

VME Bus Controller, CMOS, CPGA299, CERAMIC, PGA-299

CA91C078A-40CG Parametric

Parameter Name	Attribute value
Maker	Silicon360
Parts packaging code	PGA
package instruction	PGA,
Contacts	299
Reach Compliance Code	unknown
Address bus width	32
maximum clock frequency	40 MHz
Maximum data transfer rate	50 MBps
Drive interface standards	IEEE 1149.1
External data bus width	32
JESD-30 code	S-CPGA-P299
length	52.324 mm
Number of terminals	299
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	PGA
Package shape	SQUARE
Package form	GRID ARRAY
Maximum seat height	5.0546 mm
Maximum supply voltage	5.25 V
Minimum supply voltage	4.25 V
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	PIN/PEG
Terminal pitch	5.08 mm
Terminal location	PERPENDICULAR
width	52.324 mm
uPs/uCs/peripheral integrated circuit type	BUS CONTROLLER, VME

Preview

Download Datasheet

View All

SCV64™ User Manual

http://www.silicon360.com

Table of Contents

General Information ............................................................................................ 1-1

1.1

1.2

1.3

1.4

Introduction............................................................................................. 1-1

Product Overview ................................................................................... 1-1

1.2.1

Flexibility and Features.......................................................... 1-1

Using This Document ............................................................................. 1-4

Conventions ............................................................................................ 1-5

1.4.1

1.4.2

1.4.3

Signals .................................................................................... 1-5

Symbols.................................................................................. 1-5

Mathematical Notation........................................................... 1-5

Functional Description......................................................................................... 2-1

2.1

Introduction............................................................................................. 2-1

2.1.1

2.1.2

2.1.2.1

2.1.2.2

2.1.2.3

2.2

2.2.1

2.2.2

2.2.2.1

2.2.2.2

2.2.3

2.2.3.1

2.2.3.2

2.2.3.3

2.2.4

2.2.4.1

2.2.4.2

Organization of the Functional Description........................... 2-1

Functional Overview.............................................................. 2-2

Data Path ............................................................................... 2-2

VMEbus Interface ................................................................. 2-5

Local Bus Interface ............................................................... 2-6

Function.................................................................................. 2-8

Bus Request Modes................................................................ 2-9

Fair and Demand Modes ....................................................... 2-9

VMEbus Request Levels....................................................... 2-9

Bus Release Modes .............................................................. 2-10

Bus Clear Enabling ............................................................. 2-10

Release On Request and Release When Done .................... 2-10

Ownership Timer ................................................................ 2-11

Other Bus Release Mechanisms........................................... 2-11

Local Memory Interrupt ...................................................... 2-11

BI-Mode .............................................................................. 2-12

VMEbus Requester ................................................................................. 2-8

iii

2.2.4.3

2.3

2.3.1

2.3.1.1

2.3.1.2

2.3.1.3

2.3.2

2.4

2.4.1

2.4.1.1

2.4.2

2.4.2.1

2.4.2.2

2.4.2.3

2.4.2.4

2.5

2.5.1

2.5.2

2.5.3

2.5.3.1

2.5.3.2

2.5.3.3

2.5.4

2.5.5

2.5.6

2.5.6.1

2.5.6.2

2.5.7

2.6

2.6.1

2.6.1.1

Local and System Reset ....................................................... 2-12

VMEbus Interrupts ...............................................................2-13

Interrupt Generation............................................................. 2-13

BI-mode Effects ................................................................... 2-14

Reset Effects ........................................................................ 2-14

Local Bus Interrupts..............................................................2-15

Interrupt Enabling and Status ...............................................2-20

Local Interrupt Level Mapping............................................ 2-21

Interrupt Acknowledge Cycles .............................................2-22

Auto-Vectored Interrupts ..................................................... 2-25

Vectored Interrupts .............................................................. 2-26

BI-Mode Effects .................................................................. 2-29

Reset Effects ........................................................................ 2-29

Syscon Determination...........................................................2-30

IACK Daisy Chain Driver ....................................................2-31

VMEbus Arbiter ...................................................................2-31

Arbitration Modes............................................................... 2-31

Arbitration Time-out............................................................ 2-33

Reset Effects ........................................................................ 2-33

Bus Timer .............................................................................2-34

System Clock Driver.............................................................2-34

External Inputs ......................................................................2-34

External Status ..................................................................... 2-34

Off-Board Reset Input ......................................................... 2-35

Reset Effects on Syscon Functions .......................................2-35

SCV64 as VME Slave...........................................................2-39

Coupled Mode...................................................................... 2-39

Interrupter .............................................................................................. 2-13

Interrupt Handler ................................................................................... 2-18

System Controller Functions ................................................................. 2-30

Data Path................................................................................................ 2-36

2.6.1.2

2.6.2

2.6.2.1

2.6.2.2

2.6.2.3

2.7

2.7.1

2.7.2

2.7.2.1

2.7.2.2

2.8

2.8.1

2.8.1.1

2.8.1.2

2.8.1.3

2.8.1.4

2.8.1.5

2.8.2

2.8.2.1

2.8.2.2

2.8.2.3

2.8.3

2.8.4

2.8.5

2.8.6

2.8.7

2.8.8

2.9

2.9.1

2.9.1.1

2.9.1.2

Decoupled Mode ................................................................. 2-39

SCV64 as VME Master........................................................ 2-41

Coupled Mode..................................................................... 2-41

Decoupled Mode ................................................................. 2-42

DMA Transfers ................................................................... 2-43

CPU Memory Map............................................................... 2-45

VME Slave Memory Map.................................................... 2-49

Automatic Base Address Programming .............................. 2-51

Access Protection ................................................................ 2-52

SCV64 as VME Master........................................................ 2-53

Address Translation ............................................................ 2-53

Byte Lane Translation ......................................................... 2-54

VMEbus Mastership............................................................ 2-56

RMW Cycles....................................................................... 2-57

Termination of a Master Cycle with RETRY* ................... 2-58

SCV64 as VME Slave.......................................................... 2-58

Address Translation ............................................................ 2-58

Byte Lane Translation ......................................................... 2-59

Local Bus Mastership.......................................................... 2-60

DMA Transfers .................................................................... 2-61

Master/Slave Deadlock Resolution ...................................... 2-61

Location Monitor Access ..................................................... 2-62

Bus Busy Glitch ................................................................... 2-63

BI-Mode Effects................................................................... 2-63

Bus Error Handling .............................................................. 2-64

Local Bus Arbitration........................................................... 2-66

Local Arbiter Bypassed....................................................... 2-66

Local Arbiter Active ........................................................... 2-67

Memory Mapping ................................................................................. 2-45

VMEbus Interface ................................................................................. 2-53

Local Bus Interface ............................................................................... 2-66

CA91C078A-40CG Related Products

	CA91C078A-40CG	CA91C078A-25EG	CA91C078A-40CQ	CA91C078A-33CQ	CA91C078A-33EG	CA91C078A-33CG	CA91C078A-33IQ	CA91C078A-25IQ
Description	VME Bus Controller, CMOS, CPGA299, CERAMIC, PGA-299	VME Bus Controller, CMOS, CPGA299, CERAMIC, PGA-299	VME Bus Controller, CMOS, PQFP304, PLASTIC, QFP-304	VME Bus Controller, CMOS, PQFP304, PLASTIC, QFP-304	VME Bus Controller, CMOS, CPGA299, CERAMIC, PGA-299	VME Bus Controller, CMOS, CPGA299, CERAMIC, PGA-299	VME Bus Controller, CMOS, PQFP304, PLASTIC, QFP-304	VME Bus Controller, CMOS
package instruction	PGA,	PGA,	FQFP,	FQFP,	PGA,	PGA,	FQFP,	,
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
uPs/uCs/peripheral integrated circuit type	BUS CONTROLLER, VME	BUS CONTROLLER, VME	BUS CONTROLLER, VME	BUS CONTROLLER, VME	BUS CONTROLLER, VME	BUS CONTROLLER, VME	BUS CONTROLLER, VME	BUS CONTROLLER, VME
Maker	Silicon360	-	-	Silicon360	Silicon360	Silicon360	Silicon360	Silicon360
Parts packaging code	PGA	PGA	QFP	QFP	PGA	PGA	QFP	-
Contacts	299	299	304	304	299	299	304	-
Address bus width	32	32	32	32	32	32	32	-
maximum clock frequency	40 MHz	25 MHz	40 MHz	33 MHz	33 MHz	33 MHz	33 MHz	-
Maximum data transfer rate	50 MBps	50 MBps	50 MBps	50 MBps	50 MBps	50 MBps	50 MBps	-
Drive interface standards	IEEE 1149.1	IEEE 1149.1	IEEE 1149.1	IEEE 1149.1	IEEE 1149.1	IEEE 1149.1	IEEE 1149.1	-
External data bus width	32	32	32	32	32	32	32	-
JESD-30 code	S-CPGA-P299	S-CPGA-P299	S-PQFP-G304	S-PQFP-G304	S-CPGA-P299	S-CPGA-P299	S-PQFP-G304	-
length	52.324 mm	52.324 mm	40 mm	40 mm	52.324 mm	52.324 mm	40 mm	-
Number of terminals	299	299	304	304	299	299	304	-
Maximum operating temperature	70 °C	125 °C	70 °C	70 °C	125 °C	70 °C	85 °C	-
Package body material	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	PLASTIC/EPOXY	PLASTIC/EPOXY	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	PLASTIC/EPOXY	-
encapsulated code	PGA	PGA	FQFP	FQFP	PGA	PGA	FQFP	-
Package shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	-
Package form	GRID ARRAY	GRID ARRAY	FLATPACK, FINE PITCH	FLATPACK, FINE PITCH	GRID ARRAY	GRID ARRAY	FLATPACK, FINE PITCH	-
Maximum seat height	5.0546 mm	5.0546 mm	4.5 mm	4.5 mm	5.0546 mm	5.0546 mm	4.5 mm	-
Maximum supply voltage	5.25 V	5.5 V	5.25 V	5.25 V	5.5 V	5.25 V	-	-
Minimum supply voltage	4.25 V	4.5 V	4.25 V	4.25 V	4.5 V	4.25 V	-	-
Nominal supply voltage	5 V	5 V	5 V	5 V	5 V	5 V	5 V	-
surface mount	NO	NO	YES	YES	NO	NO	YES	-
Temperature level	COMMERCIAL	MILITARY	COMMERCIAL	COMMERCIAL	MILITARY	COMMERCIAL	INDUSTRIAL	-
Terminal form	PIN/PEG	PIN/PEG	GULL WING	GULL WING	PIN/PEG	PIN/PEG	GULL WING	-
Terminal pitch	5.08 mm	5.08 mm	0.5 mm	0.5 mm	5.08 mm	5.08 mm	0.5 mm	-
Terminal location	PERPENDICULAR	PERPENDICULAR	QUAD	QUAD	PERPENDICULAR	PERPENDICULAR	QUAD	-
width	52.324 mm	52.324 mm	40 mm	40 mm	52.324 mm	52.324 mm	40 mm	-

Recommended Resources

Desktop plastic sealing machine control circuit

Wanbao BCD-183W refrigerator circuit

Automatic battery charger circuit

A practical circuit of DAC1210

Stage strobe and photo flash dual-purpose light circuit

Broadband shortwave amplifier circuit

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components