IDTCV140 datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > IDTCV140

Preview

IDTCV140: DescriptionPROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR; File Size163KB，26 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/

Download Datasheet View All

IDTCV140 Overview

PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR

Preview

Download Datasheet

View All

IDTCV140

PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR

COMMERCIAL TEMPERATURE RANGE

PROGRAMMABLE FLEXPC

CLOCK FOR P4 PROCESSOR

IDTCV140

FEATURES:

• Power management control suitable for notebook applications

• One high precision PLL for CPU, SSC and N programming

• One high precision PLL for SRC/PCI, supports 100MHz output

frequency, SSC and N programming

• One high precision PLL for LVDS. Supports 100/96MHz output

frequency, SSC programming

• One high precision PLL for 96MHz/48MHz

• Band-gap circuit for differential outputs

• Support spread spectrum modulation, –0.5 down spread and

others

• Support SMBus block read/write, index read/write

• Selectable output strength for REF, 48MHz, PCI

• Allows for CPU frequency to change to a slower frequency to

conserve power when an application is less execution-

intensive

• Smooth transition for N programming

• Available in TSSOP package

DESCRIPTION:

IDTCV140 is a 56 pin clock device, incorporating both Intel CK410M and

CKSSCD requirements, for Intel advance P4 processors. The CPU output

buffer is designed to support up to 400MHz processor. This chip has four PLLs

inside for CPU, SRC/PCI, LVDS, and 48MHz/DOT96 IO clocks. This device

also implements Band-gap referenced I

REF

to reduce the impact of V

variation

on differential outputs, which can provide more robust system performance.

Static PLL frequency divide error can be as low as 36 ppm, worse case 114

ppm, providing high accuracy output clock. Each CPU/SRC/LVDS has its own

Spread Spectrum selection.

OUTPUTS:

•

2*0.7V current –mode differential CPU CLK pair

6*0.7V current –mode differential SRC CLK pair

One CPU_ITP/SRC selectable CLK pair

6*PCI, 2 free running, 33.3MHz

1*96MHz, 1*48MHz

1*REF

One 100/96 MHz differential LVDS

KEY SPECIFICATIONS:

• CPU/SRC CLK cycle to cycle jitter < 85ps

• PCI CLK cycle to cycle jitter < 250ps

• Static PLL frequency divide error for all clocks = 0ppm

FUNCTIONAL BLOCK DIAGRAM

PLL1

SSC

N Programmable

CPU CLK

Output Buffer

Stop Logic

CPU[1:0]

XTAL

Osc Amp

CPU_ITP/SRC7

REF

REF[1:0]

ITP_EN

LVDS CLK

Output Buffer

Stop Logic

SDATA

SCLK

SM Bus

Controller

PLL2

SSC

LVDS

PLL3

SSC

N Programmable

TT_

WRGD

#/PD

SEL100_96#

CLKREQA#

CLKREQB#

FSA.B.C

PCI_STOP#

CPU_STOP#

Control

Logic

PLL4

SEL

100/96MHz

SRC CLK

Output Buffer

Stop Logic

SRC[6:1]

PCI[3:0], PCIF[1:0]

REF

48MHz

48MHz/96MHz

Output BUffer

DOT96

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

COMMERCIAL TEMPERATURE RANGE

DECEMBER 2004

DSC 6583/7

Recommended Resources

Three voltage rectifier circuit a

Capacitor discharge high voltage power supply circuit

Simple absolute value operation circuit

Practical cooling alarm

Refrigerator compressor air cooling heat dissipation protection circuit

Circuit diagram: Fat analyzer circuit schematic_page_4

Image display problem in CCS: I use DSP for image recognition and need to display the image in CCS. I store the image pixels into memory and save them in an array, but I don't know why it cannot be displayed. I don't know what the...; fanghui20006 DSP and ARM Processors

Please help me, why can’t I use a switch to achieve forward and reverse rotation? Thank you.: #include "io430.h" #include "io430g2553.h" void Rturn() { P1DIR=BIT0+BIT2; P2DIR=BIT0+BIT1; //Make P1.0 P1.2 P2.0 P2.2 the output terminal/ //Forward rotation: A high, B low, C low, D high; // { P1OUT...; 黄磊 Microcontroller MCU

MSP430G2553 MCU Timer_A: 1. MSP430g2553 has two 16-bit timers: Timer0_A Timer1_A. Each has three capture/compare registers, with input capture and output compare functions. It can generate timer interrupts and PWM. 2. Generat...; 灞波儿奔 Microcontroller MCU

What is Warning 1478?: PIC16F1937, MPLAB X IDE V4.00, XC8 V1.41 LCD.c:70: warning: (1478) initial value for "_LCD_MODEL" differs to that in null:0 const unsigned char LCD_MODEL[][2]= //LCD modulus: 0~9, the first column is ...; liyancao001 Microchip MCU

DIY Smart Timer: [align=center][b][font=宋体][size=14.0pt]Smart Timer·[/size][/font][/b][b][size=14.0pt]DIY[/size][/b][b][font=宋体][size=14.0pt]Production[/size][/font][/b][/align][align=center]DIY&Sharing—GravityShare[/...; 万有引力平台 DIY/Open Source Hardware

Will there be timing violations if FPGA does not have timing constraints?: [align=left][font=Verdana, Helvetica, Arial, sans-serif]I would like to ask you, if I do not make any timing constraints and the compilation passes, does it mean that my registers have no timing viola...; 南盗 FPGA/CPLD

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components