4-Bit Micro-controller With LCD Driver
Features
Low power dissipation
Powerful instruction set (148 instructions)
Binary addition, subtraction, BCD
adjustment, logical operation in direct
addressing mode and index
addressing mode
Single-bit manipulation (set, reset, decision
for branch)
Various conditional branches
16 working registers and manipulation
LCD driver data transfer
Look-up table
Programmable option
System clock selection
Memory capacity
Instruction ROM capacity 2048 x 16 bits
Index ROM capacity 256 x 8 bits
Internal RAM capacity 256 x 4 bits
(low-address 128 nibbles can be accessed
by direct addressing, full-range 256 nibbles
can be accessed by index addressing)
Input/output ports
Port IOA 4 pins (with internal pull-low,
chattering clock, MUX with CX, RR, RT, RH/
SEG 37~40 by mask option)
Port IOB 4 pins (MUX with ELC, ELP, BZB,
BZ/SEG41, 42 by mask option)
Port IOC 4 pins (with internal pull-low,
low-level hold, chattering clock, MUX option
with AN1~4 by mask option)
Port IOD 4 pins (MUX with PWM1,
2/SEG33~36 by mask option)
8-level subroutine nesting
Interrupt function
External factor 2 (INT pin & port IOA, IOC
input)
Internal factor 4 (predivider, 2 timers & RFC)
Built-in EL-light driver, alarm, frequency or
melody generator (MUX with IOB/ SEG41, 42)
Built-in R to F converter circuit (MUX with
IOA/SEG37~40)
Built-in comparator, 6/8-bit PWM output, 4-bit
D/A converter, low-battery detector; this
structure can be used as a 4/6/8-bit full range
ADC
Port PWM 2 pins (MUX with SEG35, 36)
Port ADC 4 pins (MUX with IOC)
2 6-bit programmable timers with programmable
clock source
Watchdog timer
LCD/LED driver output
42 LCD/LED driver outputs (up to 168 LCD
segments are drivable)
Mask option is used to select static, 1/2 bias
1/2 duty, 1/2 bias 1/3 duty, 1/2 bias 1/4 duty,
1/3 bias 1/3 duty and 1/3 bias 1/4 duty drive
modes of the LCD panel
Mask option is used to select DC output,
and static, 1/2 duty, 1/3 duty and 1/4 duty
drive modes of the LED panel
Mask option is used to select SEG28~32 as
P open-drain DC outputs
Single instruction stops all segments that
are either in LCD or LED
Built-in voltage doubler, halver, tripler charge
pump circuit
Dual clock operation
HALT function
Stop function
General Description
APU428
is an embedded high-performance 4-bit
microcomputer with an LCD/LED driver. It contains
all the necessary functions in a single chip: 4-bit
parallel processing ALU, ROM, RAM, I/O ports, timer,
clock generator, dual clock, ADC, RFC, alarm,
EL-light, LCD driver, look-up table and watchdog
timer. The instruction set consists of 148 instructions
which include nibble operation, manipulation,
various conditional branch instructions and LCD
data transfer instructions which are powerful and
easy to follow.
The HALT function stops any internal operations other
than the oscillator, divider and LCD driver in order to
minimize the power dissipation.
The stop function stops all clocks in the chip.
Preliminary
1
Ver. 0.0
Pad No.
20
21
22
23
24
25
26
27
28
29
30
31
32
33
Pad Name
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
X
1970
1970
1970
1970
1970
1970
1970
1970
1970
1970
1970
1840
1710
1595
Y
995
1110
1225
1340
1455
1570
1685
1800
1915
2045
2175
2265
2265
2265
Pad No.
53
54
55
56
57
58
59
60
61
62
63
64
65
66
Pad Name
INT
IOM1
IOM2
IOM3
IOM4
VDD1
VDD2
VDD3
CUP1
CUP2
COM1
COM2
COM3
COM4
X
Y
70
1340
70
1225
70
1110
70
995
70
880
70
765
70
650
70
535
70
420
70
290
70
160
200
70
330
70
445
70
Chip size: 84.65 x 96.45 mil
2
Pad Descriptions
Pad Name
BAK
VDD1
VDD2
VDD3
RESET
I/O
Description
Positive back-up voltage.
In Li mode, connects a 0.1u capacitance to GND.
LCD drives the voltage and positive supply voltage.
While in Ag mode, connects +1.5V to V
DD1
.
While in Li/ExtV mode, connects +3.0V to
VDD2
.
Input pin from LSI reset request signal.
Internal pull-down resistor.
Input pin for external INT request signal.
Falling or rising edge triggered by mask option.
Internal pull-down or pull-up resistor or none is selected by mask option.
Test signal input pin.
Switching pins for supplying the LCD driving voltage to the VDD1, 2, 3 pins.
Connects the CUP1 and CUP2 pins with nonpolarized electrolytic capacitor if
1/2 or 1/3 bias mode has been selected.
In the static mode, these pins should be open.
Time-based counter frequency (clock-specified, LCD alternating frequency,
alarm signal frequency) or system clock oscillation. 32kHz crystal oscillator.
Oscillation stops at the execution of STOP instruction.
System clock oscillation.
Connected with ceramic resonator.
Connected with RC oscillation circuit.
Oscillation stops at the execution of STOP or SLOW instruction.
Output pins for supplying voltage to drive the common pins of the LCD or LED
panel.
Output pins for LCD or LED panel segment.
Input/Output port A can use software to define the internal pull-low resistor and
chattering clock in order to reduce input bounce and generate interrupt.
This port shares pins with SEG37~40 and is set by mask option.
This port also shares pins with CC, RR, RT and RH, and is set by mask option.
4
Ver. 0.0
I
INT
TESTA
CUP1
CUP2
XIN
XOUT
I
I
O
I
O
I
O
O
O
I/O
CFIN
CFOUT
COM1~4
SEG1~42
IOA1~4
Preliminary
Pad Name
IOB1~4
I/O
I/O
Description
I/O Input/Output port B.
IOB1, 2 shares pins with SEG41, 42, or ELC, ELP and is set by mask option.
IOB3, 4 shares pins with BZ, BZB and is set by mask option.
I/O Input/Output port C can use software to define the internal pull-low/
low-level hold resistor and chattering clock in order to reduce input bounce and
generate interrupt. This port shares pins with AN1-4 and is set by mask option.
Input / Output port D.
This port shares pins with SEG33~36 and is set by mask option.
IOD3,4 shares pins with PWM1,2 and is set by mask option.
1 input pin and 3 output pins for RFC application.
This port shares pins with SEG37~40 and is set by mask option.
This port shares pins with IOA1~4 and is set by mask option.
Output port for the EL-light.
These ports share pins with SEG41, 42 and are set by mask option.
These ports share pins with IOB1, 2 and are set by mask option.
Output port for alarm, frequency or melody generator.
This port shares pins with IOB3,4 and is set by mask option.
Negative supply voltage.
IOC1~4
I/O
IOD1~4
RFC
RR
RT
RH
EL
ELP
ALM
Z
GND
CC
I/O
I
O
O
O
O
O
O
O
ELC
BZB
Preliminary
5
Ver. 0.0
Embedded System
京公网安备 11010802033920号
EEWORLD
