EEWORLDEEWORLDEEWORLD

Part Number

Search

BA6-FREQ6-STBY2-SR

Description
Series - Fundamental Quartz Crystal, 10MHz Min, 20MHz Max,
CategoryPassive components    Crystal/resonator   
File Size94KB,2 Pages
ManufacturerBliley Technologies Inc
Download Datasheet Parametric View All

BA6-FREQ6-STBY2-SR Overview

Series - Fundamental Quartz Crystal, 10MHz Min, 20MHz Max,

BA6-FREQ6-STBY2-SR Parametric

Parameter NameAttribute value
MakerBliley Technologies Inc
Reach Compliance Codeunknown
Other featuresAT CUT CRYSTAL
Ageing1 PPM/YEAR
Crystal/Resonator TypeSERIES - FUNDAMENTAL
Drive level500 µW
frequency stability0.002%
frequency tolerance20 ppm
Installation featuresTHROUGH HOLE MOUNT
Maximum operating frequency20 MHz
Minimum operating frequency10 MHz
Maximum operating temperature75 °C
Minimum operating temperature
physical sizeL17.65XB7.37XH19.69 (mm)/L0.695XB0.29XH0.775 (inch)
Series resistance25 Ω
surface mountNO
Coldweld Vacuum Sealed
Although similar in appearance and configuration to a commonly used solder-sealed counterpart, Bliley's
BA
series features unexcelled process cleanliness and flux-free sealing in a vacuum to minimize
contamination. Improved aging and reliability result at a modest cost premium. The following data is
suggested for general guidance. Superior performance in temperature stability and aging can be provided
if required.
The circuit exploded, haha
Today, a customer came from Japan and brought a circuit board to Shenzhen for debugging. I looked at the circuit diagram and saw that the ground of the 5V power supply and the 220V are the same ground...
jxb01033016 Talking
Is the clock constraint hold of ispLEVER handled the same as that of xilinx?
In the tutorial of ispLEVER , there is no instruction on how to deal with the clock constraint hold in the spreadsheet . It is always blank. Question: 1/ Is the clock constraint hold of ispLEVER handl...
eeleader FPGA/CPLD
How to use VS2005 to develop applications running on winCE5.0
How to use VS2005 to develop applications running on winCE5.0...
zjl2050 Embedded System
Help solve vhdl:quartus7.2 problem encountered when running if..genarate
本人在quartus7.2运行如下vhdl代码: library ieee;use ieee.std_logic_1164.all;entity shift isgeneric (len:integer);port(a,clk:in std_logic;b:out std_logic);end shift;architecture behav of shift iscomponent dffpor...
kittenqq Embedded System
Thinking about whether the result of FPGA compilation can be converted into source code?
1. Can the .POF and .SOF files compiled by FPGA be converted to VHDL or VERILOG? Or can the .JED files compiled by XILINX be converted to VHDL or VERILOG? I think if this problem can be reversed, it s...
eeleader FPGA/CPLD
Upload the MINI board data based on STM32F103RBT6!
[backcolor=rgb(238, 238, 238)][size=12px]This is a MINI development board with STM32F103RBT6 as the controller and equipped with CAN bus and RS485 bus interfaces. It is suitable for beginners to learn...
jiaxinhui2011 stm32/stm8

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 243  2039  1881  1874  1191  5  42  38  24  55 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号