LSI/CSI
UL
®
LS7183/LS7184
(631) 271-0400 FAX (631) 271-0405
July 2005
LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747
A3800
QUADRATURE CLOCK CONVERTER
FEATURES:
• x1, x2 and x4 resolution
• Programmable output pulse width (200ns to 140µs)
• Excellent regulation of output pulse width
• TTL and low voltage CMOS compatible I/Os
• +3V to +5.5V operation (V
DD
- V
SS
)
• LS7183, LS7184 (DIP);
LS7183-S, LS7184-S (SOIC) - See Figure 1
DESCRIPTION:
The LS7183 and LS7184 are CMOS quadrature clock con-
verters. Quadrature clocks derived from optical or magnetic
encoders, when applied to the A and B inputs of the LS7183/
LS7184, are converted to strings of Up Clocks and Down
Clocks (LS7183) or to a Clock and an Up/Down direction
control (LS7184). These outputs can be interfaced directly
with standard Up/Down counters for direction and position
sensing of the encoder.
INPUT/OUTPUT DESCRIPTION:
RBIAS
(Pin 1)
Input for external component connection. A resistor connected
between this input and V
SS
adjusts the output clock pulse
width (Tow).
V
DD
(Pin 2)
Supply Voltage positive terminal.
V
SS
(Pin 3
)
Supply Voltage negative terminal.
A, B
(Pin 4, Pin 5)
Quadrature Clock inputs A and B. Directional output pulses are
generated from the A and B clocks according to Fig. 2. A and B
inputs have built-in immunity for noise signals less than 50ns
duration (Validation delay, T
VD
). The A and B inputs are in-
hibited during the occurrence of a directional output clock
(UPCK or DNCK), so that spurious clocks resulting from en-
coder dither are rejected.
PIN ASSIGNMENT - TOP VIEW
RBIAS
V
DD(+V)
1
8
7
6
UPCK
LSI
LS7183
2
3
4
DNCK
MODE
V
SS(-V)
A
5
B
RBIAS
V
DD(+V)
1
2
3
8
7
6
CLK
LSI
LS7184
UP/DN
MODE
V
SS(-V)
A
4
5
B
FIGURE 1
LS7183 - DNCK
(Pin 7)
In LS7183, this is the DOWN Clock Output. This output
consists of low-going pulses generated when A input
lags the B input.
LS7184 - UP/DN
(Pin 7)
In LS7184, this is the count direction indication output.
When A input leads the B input, the UP/DN output goes
high indicating that the count direction is UP. When A
input lags the B input, UP/DN output goes low,
indicating that the count direction is DOWN.
LS7183 - UPCK
(Pin 8)
In LS7183, this is the UP Clock output. This output con-
sists of low-going pulses generated when A input leads
the B input.
MODE
(Pin 6)
MODE is a 3-state input to select resolution x1, x2 or x4. The
input quadrature clock rate is multiplied by factors of 1, 2 and 4
in x1, x2 and x4 mode respectively in producing the output
LS7184 - CLK
(Pin 8)
UP/DN clocks (See Fig. 2). x1, x2 and x4 modes selected by In LS7184, this is the combined UP Clock and DOWN
the MODE input logic levels are as follows:
Clock output. The count direction at any instant is
indicated by the UP/DN output (Pin 7).
Mode = 0
: x1 selected
Mode = 1
: x2 selected
NOTE:
For the LS7184, the timing of CLK and UP/DN
Mode = Float : x4 selected
requires that the counter interfacing with LS7184 counts
on the rising edge of the CLK pulses.
7183/84-072705-1
FORWARD
A
T
PW
T
PS
B
T
DS
UPCLK
(7183LV)
DNCLK
(7183LV)
CLK
(7184LV)
UP/DN
(7184LV)
2
4
2
4
T
OW
2
1
4
2
T
PS
REVERSE
4
1
4
2
1
4
2
2
4
1
4
2
NOTE:
Output clocks labelled 1, 2 and 4 have the following interpretations.
1: Generated in x1, x2 and x4 modes
2: Generated in x2 and x4 modes only
4: Generated in x4 mode only
FIGURE 2. LS7183, LS7184 INPUT/OUTPUT TIMING
A
4
FILTER
INHIBIT
LOGIC
DIRECTION
8 UPCK or CLK
MUX
AND
BUFFER
B
5
FILTER
7
DNCK or UP/DN
RBIAS
1
CURRENT
MIRROR
PULSE
V
DD
1M
MODE
6
1M
MODE
DECODE
V
DD
V
SS
2
3
FIGURE 3. LS7183, LS7184 BLOCK DIAGRAM
The information included herein is believed to be
accurate and reliable. However, LSI Computer Systems,
Inc. assumes no responsibilities for inaccuracies, nor for
any infringements of patent rights of others which may
result from its use.
7183/84-012703-3
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