LS7183 / LS7184
Description:
Encoder to Counter Interface Chips
Features:
X4, X2 or X1 resolution multiplication
TTL and CMOS compatible
Low power (micro-amps)
8-pin DIP or SOIC package
No external clocks required
Drive standard Up/Dn counters
Monolithic CMOS
Operates from 3V to 5V power supply
The
LS7183
and
LS7184
provide an interface between industry standard A and B quadrature incremental
encoder outputs to standard up/down counters. The
LS7183
outputs can connect directly to the up and
down clock inputs of counters such as 74193 or 40193. The
LS7184
outputs can connect directly to the
Clock and Up/Dn inputs of counters such as 4516 or 74169.
The
LS7183
and
LS7184
are improved designs over the
LS7083
and
LS7084
products and should be
considered first for all new product designs. The primary differences between the old and new LS chips
are the addition of a X2 resolution multiplication, power supply operating range and improved output pulse
timing characteristics.
Please Note:
Rbias values for output pulse width timing are not the same as the
LS7083
and
LS7084
values.
Absolute Maximum Ratings:
Parameter
Operating Temperature
Storage Temperature
Voltage @ Any Input
Supply Voltage (VCC)
Min.
-20
-55
-.3
Max.
85
150
VCC+.3
7
Units
°C
°C
Volts
Volts
Optical Encoder
Rbias
1
+VDC
2
Gnd
3
A in
4
LS7183
74193
4
type
DnClk out
7
Cascadable
6
Mode input
Up/Dn
+VDC Counter
5
B in
Float
8
UpClk out
5
Top View
Rbias
1
+VDC
2
Gnd
3
A in
4
8
Clock out
7
Up/Dn out
6
Mode input
5
B in
15
10
Optical Encoder
LS7184
4516
type
Cascadable
+VDC
Float
Up/Dn
Counter
Top View
Pin Descriptions:
Pin 1 (Rbias Input):
Input for external component connection. A resistor connected between this input and ground adjusts the output pulse width. See Rbias Resistor Value vs.
Timing Table for further information.
Pins 4 & 5 (A & B Inputs):
Connect to the A and B quadrature outputs of the encoder. Both inputs have debounce filters. Minimum pulse width is set at 300ns. There is no maximum limit.
Input current is less than 1µA. The A and B inputs can be swapped to reverse the direction of the external counters.
Pin 6 (Mode Input):
Mode is a 3-state input to select resolution X1, X2 or X4. The input quadrature clock rate is multiplied by factors of 1, 2 or 4 in X1, X2 or X4 modes respectively
in producing the output Up/Dn clocks. X1, X2 or X4 modes are selected by input logic levels as follows:
Mode = 0 VDC = X1 Selection
Mode = +VDC = X2 Selection
Mode = Float = X4 Selection
In X4 mode, one pulse is generated for each A/B state change. In X1 mode, one pulse is generated per quadrature cycle. In X2, two pulses per quadrature cycle.
LS7183 Pin 7 (Down Clock Output):
Normally high, low-true. The low level pulse width is set by pin 1. Down counts are enabled only when B leads A.
LS7184 Pin 7 (Up/Down Clock Output):
This output steers the external counter up or down. High = Up (A leads B), Low = Down (B leads A).
LS7183 Pin 8 (Up Clock Output):
Normally high, low-true. The low level pulse width is set by pin 1. Up counts are enabled only when A leads B.
LS7184 Pin 8 (Clock Output):
Normally high, low-true. The low level pulse width is set by pin 1. The external counter should count on the rising (high-going) edge of this output.
Surface Mount Package:
The 8-pin SOIC package has the same pin-out as the DIP version shown above.
US
digital
info@usdigital.com www.usdigital.com
Local: 360.260.2468 Sales: 800.736.0194
Support: 360.397.9999 Fax: 360.260.2469
1400 NE 136th Ave.
Vancouver, Washington
98684
USA
page
1
LS7183 / LS7184
LS7183 Timing Diagram:
A Leads B
CH A
CH B
X1 Mode
UpClk
DnClk
UpClk
X2 Mode
DnClk
UpClk
X4 Mode
DnClk
Encoder to Counter Interface Chips
Stopped
B Leads A
LS7184 Timing Diagram:
A Leads B
Stopped
B Leads A
CH A
CH B
(X1 Mode) Clock
(X2 Mode) Clock
(X4 Mode) Clock
Up/Dn
Timing Diagram Notes:
The maximum time delay from the A or B input to the leading edge of any output is 270ns for 3VDC operation and 150ns for 5VDC
operation. The pulse width of all clock outputs is set by the value of the Rbias resistor as shown in the table above. Typical rise or
fall time of each logic output 10 to 20ns.
Ordering Information:
DIP Package (300mil):
LS7183-DIP
or
LS7184-DIP
SOIC Package:
LS7183-SOIC
or
LS7184-SOIC
Price:
$3.20 / 1
$2.57 / 25
$2.05 / 100
$1.73 / 500
$1.47 / 1K
Technical Data, Rev. 07.12.06, July 2006
All information subject to change without notice.
US
digital
info@usdigital.com www.usdigital.com
Local: 360.260.2468 Sales: 800.736.0194
Support: 360.397.9999 Fax: 360.260.2469
1400 NE 136th Ave.
Vancouver, Washington
98684
USA
page
3
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