LSI/CSI
UL
®
LS7211-7212
(631) 271-0400 FAX (631) 271-0405
November 2003
LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747
A3800
PROGRAMMABLE DIGITAL DELAY TIMER
FEATURES:
• 8-bit programmable delay from microseconds to days
• On chip oscillator (RC or Crystal) or external clock time base
• Selectable prescaler for real time delay generation based
on 50Hz/60Hz time base or 32.768kHz watch crystal
• Four operating modes
• Reset input for delay abort
• Low quiescent and operating current
• Direct relay drive
• +4V to +18V operation (V
DD
- V
SS
)
• LS7211, LS7212 (DIP); LS7211-S, LS7212-S (SOIC) - See Figure 1
DESCRIPTION:
The LS7211 and LS7212 are CMOS integrated circuits for
generating digitally programmable delays. The delay is
controlled by 8 binary weighted inputs, WB0 - WB7, in con-
junction with an applied clock or oscillator frequency. The
programmed time delay manifests itself in the Delay Output
(OUT) as a function of the Operating Mode selected by the
Mode Select inputs A and B: One-Shot, Delayed Operate,
Delayed Release or Dual Delay. The time delay is initiated
by a transition of the Trigger Input (TRIG).
I/O DESCRIPTION:
MODE SELECT Inputs A & B
(Pins 1 & 2)
The 4 operating modes are selected by Inputs A and B
according to Table 1
TABLE 1. MODE SELECTION
A
0
0
1
1
B
0
1
0
1
MODE
One-Shot (OS)
Delayed Operate (DO)
Delayed Release (DR)
Dual Delay (DD)
A
B
V
DD
(+V)
RC/CLOCK
RCS/CLKS
PSCLS
RESET
V
SS
(-V)
OUT
1
2
3
18
17
16
PIN ASSIGNMENT - TOP VIEW
TRIG
WB0
WB1
WB2
WB3
WB4
WB5
WB6
WB7
LSI
LS7211
4
5
6
7
8
9
15
14
13
12
11
10
A
B
V
DD
(+V)
XTLI/CLOCK
XTLO
PSCLS
RESET
V
SS
(-V)
OUT
1
2
18
17
16
15
14
13
12
11
10
TRIG
WB0
WB1
WB2
WB3
WB4
WB5
WB6
WB7
3
4
5
6
7
8
9
LSI
LS7212
FIGURE 1
Each input has an internal pull-up resistor of about 500kΩ.
One-Shot Mode (OS)
A positive transition at the TRIG input causes OUT to
switch low without delay and starts the delay timer. At the
end of the programmed delay timeout, OUT switches high.
If a delay timeout is in progress when a positive transition
occurs at the TRIG input, the delay timer will be restarted.
A negative transition at the TRIG input has no effect.
Delayed Operate Mode (DO)
A positive transition at the TRIG input starts the delay tim-
er. At the end of the delay timeout, OUT switches low. A
negative transition at the TRIG input causes OUT to switch
high without delay. OUT is high when TRIG is low.
7211-110503-1
Delayed Release Mode (DR)
A negative transition at the TRIG input starts the delay tim-
er. At the end of the delay timeout, OUT switches high. A
postive transition at the TRIG input causes OUT to switch
low without delay. OUT is low when TRIG is high.
Dual Delay Mode (DD)
A positive or negative transition at the TRIG input starts
the delay timer. At the end of the delay timeout, OUT
switches to the logic state which is the inverse of the TRIG
input. If a delay timeout is in progress when a transition
occurs at the TRIG input, the delay timer is restarted.
TRIGGER Input
(TRIG, Pin 18)
A transition at the TRIG input causes OUT to switch with or
without delay, depending on the selected mode. The TRIG
input to OUT transition relation is always opposite in po-
larity, with the exception of One-Shot mode. (See Mode
definitions above.) TRIG input has an internal pull-down re-
sistor of about 500kΩ and is buffered by a Schmitt trigger to
provide input hysterisis.
LS7211 TIME BASE Input
(RC/CLOCK, Pin 4)
For LS7211, the basic timing signal is applied at the RC/
CLOCK input. The clock can be provided from either an ex-
ternal source or generated by an internal oscillator by con-
necting an R-C network to this input.
The frequency of oscillation is given by
ƒ 1/RC.
Chip-to-
chip oscillation tolerance is ± 5% for a fixed value of RC.
The minimum resistance, R
MIN
= 4000Ω, V
DD
= + 4V
= 1200Ω, V
DD
= +10V
= 600Ω, V
DD
= +18V
The external clock mode is selected by applying a logic low
to the RCS/CLKS input (Pin 5); the internal oscillator mode
is selected by applying a high level to the RCS/CLKS input.
LS7212 TIME BASE Input
(XTLI/CLOCK, Pin 4)
For LS7212, the basic timing clock is applied to the XLTI/
CLOCK input from either an external clock source or gener-
ated by an internal crystal oscillator by connecting a crystal
between XTLI/CLOCK input and the XTLO output (Pin 5).
LS7211 TIME BASE SELECT Input
(RCS/CLKS, Pin 5)
For LS7211, the external clock operation at Pin 4 is se-
lected by applying a logic low to the RCS/CLKS input. The
internal oscillator option with RC timer at Pin 4 is selected
by applying a logic high at the RCS/CLKS input. RCS/CLKS
input has an internal pull-down resistor of about 500KΩ.
LS7212 TIME BASE Output
(XTLO, Pin 5)
For LS7212, when a crystal is used for generating the time
base oscillation, the crystal is connected between XTLI/
CLOCK and XTLO pins.
PRESCALER SELECT Input
(PSCLS, Pin 6)
The PSCLS input is a 3-state input, which selects one of
three prescale factors according to Table 2.
TABLE 2. PRESCALE FACTOR SELECTION
PSCLS Input
Logic Level
Float
Low
High
S (Prescale Factor )
LS7211
LS7212
1
1
3000
32768
3600
32768x60
TIMER RESET Input
(RESET, Pin 7)
When RESET input switches high, any timeout in progress
is aborted and OUT switches high without delay. With RE-
SET high, OUT remains high. When RESET switches low
with TRIG low in any mode, OUT remains high. When RE-
SET switches low with TRIG high in Delayed Operate and
Dual Delay modes, the delay timer is started and OUT
switches low at the end of the delay timeout. When RE-
SET switches low with TRIG high in Delayed Release
mode, OUT switches low without delay. When RESET
switches low with TRIG high in One-Shot mode, OUT re-
mains high. RESET input has an internal pull-down resistor
of about 500kΩ.
V
SS
(-V, Pin 8)
Supply voltage negative terminal or GND.
DELAY Output
(OUT, Pin 9)
Except in One-Shot mode, OUT switches with or without
delay (depending on mode) in inverse relation to the logic
level of the TRIG input. In One-Shot mode, a timed low
level is produced at OUT, in response to a positive transi-
tion of the TRIG input.
WEIGHTING BIT Inputs
(WB7 to WB0, Pins 10 - 17)
Inputs WB0 through WB7 are binary weighted delay bits
used to program the delay according to the following
relations:
One-Shot Mode: Pulse width = SW
ƒ
All other Modes: Delay = SW + 0.5
ƒ
Where:
S = Prescale factor (See Table 2)
ƒ = Time base frequency at Pin 4
W = WB0 + WB1 + ....... WB7
The weighting factor W is calculated by substituting in the
equation above for W, the weighted values for all the WB
inputs that are at logic high. The weighted values for the
WB inputs are shown in Table 3. Each WB input has an in-
ternal pull-down resistor of about 500kΩ.
TABLE 3. BIT WEIGHTS
BITS
WB0
WB1
WB2
WB3
WB4
WB5
WB6
WB7
VALUE
1
2
4
8
16
32
64
128
Using prescale factors of 3000 and 3600, delays in units of
minutes can be produced from 50Hz and 60Hz line sourc-
es. Prescale factors of 32,768 and 32,768 x 60 can be used
to generate accurate delays in units of seconds and min-
utes, respectively, from a 32kHz watch crystal.
V
DD
(+V, Pin 3)
Supply voltage positive terminal.
7211-012703-2
t
0
Clock
t
1
TRIG
t
2
A,B
t
3
WB0-WB7
OUT
A = 0, B = 1, Delayed Operate
Programmed Delay
t
4
t
4
t
1
Immediate Release
Note 1.
TRIG input is clocked in by the negative edge of external clock.
Note 2.
Inputs A, B and WB0 - WB7 are sampled only at a TRIG input trainsition and ignored at all other times.
Note 3.
OUT is switched by the positive edge of the external clock.
FIGURE 3. INPUT/OUTPUT TIMING
TRIG
F
RESET
OUT(OS)
C
OUT(DO)
OUT(DR)
D
OUT(DD)
G
A
B
E
H
A.
Turn-on delay in DO and DD modes; Pulse-width in OS mode.
B.
Turn-off delay in DR and DD modes.
C.
Pulse-width extended by re-trigger in OS mode.
No effect in DO and DD modes because TRIG switches back low before turn-on delay has timed out.
D.
Turn-off delay in DR mode.
E.
Turn-on delay in DO and DD modes; pulse-width in OS mode.
F.
No effect in DO, DR and DD modes because of TRIG’s switching back to opposite levels.
G.
Time-outs aborted and OUT forces high by RESET.
H.
After the removal of RESET, OUT switches to the inverse polarity of TRIG
immediately (DR) or after the timeout (DO, DD). No effect in OS.
FIGURE 4. MODE ILLUSTRATION WITH TRIG, OUT AND RESET
7211-012703-5
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