AT25DF161-MHF-Y datasheet, PDF

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AT25DF161-MHF-Y: DescriptionFlash, 2MX8, PDSO8,; Categorystorage storage; File Size3MB，52 Pages; ManufacturerAdesto Technologies; Environmental Compliance

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AT25DF161-MHF-Y Overview

Flash, 2MX8, PDSO8,

AT25DF161-MHF-Y Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Adesto Technologies
package instruction	HVSON, SOLCC8,.25
Reach Compliance Code	compliant

AT25DF161-MHF-Y Preview

Features

•

Single 2.3V - 3.6V or 2.7V - 3.6V Supply

•

Serial Peripheral Interface (SPI) Compatible

– Supports SPI Modes 0 and 3

– Supports RapidS Operation

– Supports Dual-Input Program and Dual-Output Read

Very High Operating Frequencies

– 100MHz for RapidS

– 85MHz for SPI

– Clock-to-Output (t

) of 5ns Maximum

Flexible, Optimized Erase Architecture for Code + Data Storage Applications

– Uniform 4-Kbyte Block Erase

– Uniform 32-Kbyte Block Erase

– Uniform 64-Kbyte Block Erase

– Full Chip Erase

Individual Sector Protection with Global Protect/Unprotect Feature

– 32 Sectors of 64-Kbytes Each

Hardware Controlled Locking of Protected Sectors via WP Pin

Sector Lockdown

– Make Any Combination of 64-Kbyte Sectors Permanently Read-Only

128-Byte Programmable OTP Security Register

Flexible Programming

– Byte/Page Program (1- to 256-Bytes)

Fast Program and Erase Times

– 1.0ms Typical Page Program (256-Bytes) Time

– 50ms Typical 4-Kbyte Block Erase Time

– 250ms Typical 32-Kbyte Block Erase Time

– 400ms Typical 64-Kbyte Block Erase Time

Program and Erase Suspend/Resume

Automatic Checking and Reporting of Erase/Program Failures

Software Controlled Reset

JEDEC Standard Manufacturer and Device ID Read Methodology

Low Power Dissipation

– 5mA Active Read Current (Typical at 20MHz)

– 5µA Deep Power-Down Current (Typical)

Endurance: 100,000 Program/Erase Cycles

Data Retention: 20 Years

Complies with Full Industrial Temperature Range

Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options

– 8-lead SOIC (150-mil and 208-mil wide)

– 8-pad Ultra Thin DFN (5 x 6 x 0.6mm)

•

16-Megabit

2.3V or 2.7V

Minimum

SPI Serial Flash

Memory

AT25DF161

•

3687G–DFLASH–1/2013

Description

The AT25DF161 is a serial interface Flash memory device designed for use in a wide variety of high-volume consumer

based applications in which program code is shadowed from Flash memory into embedded or external RAM for execution.

The flexible erase architecture of the AT25DF161, with its erase granularity as small as 4-Kbytes, makes it ideal for data

storage as well, eliminating the need for additional data storage EEPROM devices.

The physical sectoring and the erase block sizes of the AT25DF161 have been optimized to meet the needs of today's

code and data storage applications. By optimizing the size of the physical sectors and erase blocks, the memory space can

be used much more efficiently. Because certain code modules and data storage segments must reside by themselves in

their own protected sectors, the wasted and unused memory space that occurs with large sectored and large block erase

Flash memory devices can be greatly reduced. This increased memory space efficiency allows additional code routines and

data storage segments to be added while still maintaining the same overall device density.

The AT25DF161 also offers a sophisticated method for protecting individual sectors against erroneous or malicious

program and erase operations. By providing the ability to individually protect and unprotect sectors, a system can

unprotect a specific sector to modify its contents while keeping the remaining sectors of the memory array securely

protected. This is useful in applications where program code is patched or updated on a subroutine or module basis, or in

applications where data storage segments need to be modified without running the risk of errant modifications to the

program code segments. In addition to individual sector protection capabilities, the AT25DF161 incorporates Global Protect

and Global Unprotect features that allow the entire memory array to be either protected or unprotected all at once. This

reduces overhead during the manufacturing process since sectors do not have to be unprotected one-by-one prior to

initial programming.

To take code and data protection to the next level, the AT25DF161 incorporates a sector lockdown mechanism that allows

any combination of individual 64-Kbyte sectors to be locked down and become permanently read-only. This addresses the

need of certain secure applications that require portions of the Flash memory array to be permanently protected against

malicious attempts at altering program code, data modules, security information, or encryption/decryption algorithms, keys,

and routines. The device also contains a specialized OTP (One-Time Programmable) Security Register that can be used for

purposes such as unique device serialization, system-level Electronic Serial Number (ESN) storage, locked key storage,

etc.

Specifically designed for use in 3V systems, the AT25DF161 supports read, program, and erase operations with a supply

voltage range of 2.3V to 3.6V or 2.7V to 3.6V. No separate voltage is required for programming and erasing.

AT25DF161

3687G–DFLASH–1/2013

AT25DF161

Pin Descriptions and Pinouts

Pin Descriptions

Name and Function

CHIP SELECT:

Asserting the CS pin selects the device. When the CS pin is deasserted, the device

will be deselected and normally be placed in standby mode (not Deep Power-Down mode), and the

SO pin will be in a high-impedance state. When the device is deselected, data will not be accepted on

the SI pin.

A high-to-low transition on the CS pin is required to start an operation, and a low-to-high transition is

required to end an operation. When ending an internally self-timed operation such as a program or

erase cycle, the device will not enter the standby mode until the completion of the operation.

SERIAL CLOCK:

This pin is used to provide a clock to the device and is used to control the flow of

data to and from the device. Command, address, and input data present on the SI pin is always latched

in on the rising edge of SCK, while output data on the SO pin is always clocked out on the falling edge

of SCK.

SERIAL INPUT (SERIAL INPUT/OUTPUT):

The SI pin is used to shift data into the device. The SI

pin is used for all data input including command and address sequences. Data on the SI pin is always

latched in on the rising edge of SCK.

With the Dual-Output Read Array command, the SI pin becomes an output pin (SIO) to allow two bits

of data (on the SO and SIO pins) to be clocked out on every falling edge of SCK. To maintain

consistency with SPI nomenclature, the SIO pin will be referenced as SI throughout the document

with exception to sections dealing with the Dual-Output Read Array command in which it will be

referenced as SIO.

Data present on the SI pin will be ignored whenever the device is deselected (CS is deasserted).

SERIAL OUTPUT (SERIAL OUTPUT/INPUT):

The SO pin is used to shift data out from the device.

Data on the SO pin is always clocked out on the falling edge of SCK.

With the Dual-Input Byte/Page Program command, the SO pin becomes an input pin (SOI) to allow

two bits of data (on the SOI and SI pins) to be clocked in on every rising edge of SCK. To maintain

consistency with SPI nomenclature, the SOI pin will be referenced as SO throughout the document

with exception to sections dealing with the Dual-Input Byte/Page Program command in which it will

be referenced as SOI.

The SO pin will be in a high-impedance state whenever the device is deselected (CS is deasserted).

WRITE PROTECT:

The WP pin controls the hardware locking feature of the device. Please refer to

“Protection Commands and Features” on page 18

for more details on protection features and the WP

pin.

The WP pin is internally pulled-high and may be left floating if hardware controlled protection will not

be used. However, it is recommended that the WP pin also be externally connected to V

whenever

possible.

HOLD:

The HOLD pin is used to temporarily pause serial communication without deselecting or

resetting the device. While the HOLD pin is asserted, transitions on the SCK pin and data on the SI pin

will be ignored, and the SO pin will be in a high-impedance state.

The CS pin must be asserted, and the SCK pin must be in the low state in order for a Hold condition to

start. A Hold condition pauses serial communication only and does not have an effect on internally self-

timed operations such as a program or erase cycle. Please refer to

“Hold” on page 39

for additional

details on the Hold operation.

The HOLD pin is internally pulled-high and may be left floating if the Hold function will not be used.

However, it is recommended that the HOLD pin also be externally connected to V

whenever

possible.

DEVICE POWER SUPPLY:

The V

pin is used to supply the source voltage to the device.

Operations at invalid V

voltages may produce spurious results and should not be attempted.

GROUND:

The ground reference for the power supply. GND should be connected to the system

ground.

Table 2-1.

Symbol

Asserted

State

Type

Low

Input

SCK

Input

SI (SIO)

Input/Output

SO (SOI)

Output/Input

Low

Input

HOLD

Low

Input

GND

Power

3687G–DFLASH–1/2013

Figure 2-1.

Pin Configurations

8-SOIC

8-UDFN

SO (SOI)

GND

HOLD

SCK

SI (SIO)

SO (SOI)

GND

HOLD

SCK

SI (SIO)

Top View

Block Diagram

Figure 3-1.

Block Diagram

CONTROL AND

PROTECTION LOGIC

I/O BUFFERS

AND LATCHES

SCK

SI (SIO)

SO (SOI)

INTERFACE

CONTROL

AND

LOGIC

ADDRESS LATCH

SRAM

DATA BUFFER

Y-DECODER

Y-GATING

X-DECODER

HOLD

FLASH

MEMORY

ARRAY

Memory Array

To provide the greatest flexibility, the memory array of the AT25DF161 can be erased in four levels of granularity including

a full chip erase. In addition, the array has been divided into physical sectors of uniform size, of which each sector can be

individually protected from program and erase operations. The size of the physical sectors is optimized for both code and

data storage applications, allowing both code and data segments to reside in their own isolated regions. The Memory

Architecture Diagram illustrates the breakdown of each erase level as well as the breakdown of each physical sector.

AT25DF161

3687G–DFLASH–1/2013

AT25DF161

Figure 4-1.

Memory Architecture Diagram

3687G–DFLASH–1/2013

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AT25DF161-MHF-Y Related Products

	AT25DF161-MHF-Y	AT25DF161-SSHF-B	AT25DF161-SHF-T
Description	Flash, 2MX8, PDSO8,	Flash, 2MX8, PDSO8,	Flash, 2MX8, PDSO8,
Is it Rohs certified?	conform to	conform to	conform to
Maker	Adesto Technologies	Adesto Technologies	Adesto Technologies
package instruction	HVSON, SOLCC8,.25	SOP, SOP8,.25	SOP, SOP8,.3
Reach Compliance Code	compliant	compliant	compliant

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