TSPC603EVAU2LN datasheet, PDF - EEWORLD Datasheet

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TSPC603EVAU2LN: DescriptionMicroprocessor,; CategoryThe embedded processor and controller Microcontrollers and processors; File Size562KB，38 Pages; ManufacturerThomson-CSF Compsants Specific

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TSPC603EVAU2LN Parametric

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Maker	Thomson-CSF Compsants Specific
package instruction	,
Reach Compliance Code	unknown

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TSPC603E

PowerPC 603e™ RISC MICROPROCESSOR Family

PID6-603e Specification

DESCRIPTION

The PID6-603e implementation of PC603e (after named 603e)

is a low-power implementation of reduced instruction set com-

puter (RISC) microprocessors PowerPC™ family. The 603e

implements 32-bit effective addresses, integer data types of 8,

16 and 32 bits, and floating-point data types of 32 and 64 bits.

The 603e is a low-power 3.3-volt design and provides four soft-

ware controllable power-saving modes.

The 603e is a superscalar processor capable of issuing and

retiring as many as three instructions per clock. Instructions

can execute out of order for increased performance ; however,

the 603e makes completion appear sequential. The 603e inte-

grates five execution units and is able to execute five instruc-

tions in parallel.

The 603e provides independent on-chip, 16-Kbyte, four-way

set-associative, physically addressed caches for instructions

and data and on-chip instruction and data memory manage-

ment units (MMUs). The MMUs contain 64-entry, two-way set-

associative, data and instruction translation lookaside buffers

that provide support for demand-paged virtual memory

address translation and variable-sized block translation.

The 603e has a selectable 32 or 64-bit data bus and a 32-bit

address bus. The 603e interface protocol allows multiple mas-

ters to complete for system resources through a central exter-

nal arbiter. The 603e supports single-beat and burst data

transfers for memory accesses, and supports memory-

mapped I/O.

The 603e uses an advanced, 3.3-V CMOS process technology

and maintains full interface compatibility with TTL devices.

The 603e integrates in system testability and debugging fea-

tures through JTAG boundary-scan capability.

CERQUAD 240

A suffix

CERQUAD 240

Ceramic Leaded Chip Carrier

MAIN FEATURES

2.4 SPECint95, 2.1 SPECfp95 @ 100 MHz (estimated)

Superscalar (3 instructions per clock peak).

Dual 16KB caches.

Selectable bus clock.

32-bit compatibility PowerPC implementation.

On chip debug support.

typical = 3.2 Watts (100 MHz), full operating conditions.

Nap, doze and sleep modes for power savings.

Branch folding.

64-bit data bus (32-bit data bus option).

4-Gbyte direct addressing range.

Pipelined single/double precision float unit.

IEEE 754 compatible FPU.

IEEE P 1149-1 test mode (JTAG/C0P).

int

max = 100/120/133 MHz.

bus

max = 66 MHz.

Compatible CMOS input

TTL Output.

G suffix

CBGA 255

Ceramic Ball Grid Array

SCREENING / QUALITY / PACKAGING

This product is manufactured in full compliance with :

MIL-STD-883 class B or According to TCS standards

Upscreenings based upon TCS standards

Full military temperature range (T

= -55°C, T

= +125°C)

Industrial temperature range (T

–

40°C, T

= +110°C)

= 3.3 V

5 %.

240 pin Cerquad or 255 pin CBGA packages

December1998

1/38

TSPC603E

A. GENERAL DESCRIPTION

Fetch

Unit

Completion

Unit

Dispatch

Unit

Branch

Unit

Integer

Unit

Gen

Reg

Unit

Gen

Re-

name

Load/

Store

Unit

Re-

name

Reg

File

Float

Unit

D MMU

16K Data Cache

I MMU

16K Inst. Cache

Bus Interface Unit

32b

address

System Bus

64b

data

Figure 1 : Block diagram

1. INTRODUCTION

The 603e is a low-power implementation of the PowerPC microprocessor family of reduced instruction set commuter (RISC) micro-

processors. The 603e implements the 32-bit portion of the PowerPC architecture, which provides 32-bit effective addresses, integer

data types of 8, 16 and 32 bits, and floating-point data types of 32 and 64 bits. For 64-bit PowerPC microprocessors, the PowerPC

architecture provides 64-bit integer data types, 64-bit addressing, and other features required to complete the 64-bit architecture.

The 603e provides four software controllable power-saving modes. Three of the modes (the nap, doze, and sleep modes) are static in

nature, and progressively reduce the amount of power dissipated by the processor. The fourth is a dynamic power management

mode that causes the functional units in the 603e to automatically enter a low-power mode when the functional units are idle without

affecting operational performance, software execution, or any external hardware.

The 603e is a superscalar processor capable of issuing and retiring as many as three instructions per clock. Instructions can execute

out of order for increased performance ; however, the 603e makes completion appear sequential.

The 603 e integrates five execution units - an integer unit (IU), a floating-point unit (FPU), a branch processing unit (BPU), a load/store

unit (LSU) and a system register unit (SRU). The ability to execute five instructions in parallel and the use of simple instructions with

rapid execution times yield high efficiency and throughput for 603e-based systems. Most integer instructions execute in one clock

cycle. The FPU is pipelined so a single-precision multiply-add instruction can be issued every clock cycle.

The 603e provides independent on-chip, 16 Kbyte, four-way set-associative, physically addressed caches for instructions and data

and on-chip instruction and data memory management units (MMUs). The MMUs contain 64-entry, two-way set-associative, data

and instruction translation lookaside buffers (DTLB and ITLB) that provide support for demand-paged virtual memory address

translation and variable-sized block translation. The TLBs and caches use a least recently used (LRU) replacement algorithm. The

603e also supports block address translation through the use of two independent instruction and data block address translation (IBAT

and DBAT) arrays of four entries each. Effective addresses are compared simultaneously with all four entries in the BAT array during

block translation. In accordance with the PowerPC architecture, if an effective address hits in both the TLB and BAT array, the BAT

translation takes priority.

The 603e has a selectable 32 - or 64-bit - data bus and a 32-bit address bus. The 603e interface protocol allows multiple masters to

compete for system resources through a central external arbiter. The 603e provides a three-state coherency protocol that supports

the exclusive, modified, and invalid cache states. This protocol as a compatible subset of the MESI (modified/exclusive/shared/in-

valid) four-state protocol and operates coherently in systems that contain four-state caches. The 603e supports single-beat and burst

data transfers for memory accesses, and supports memory-mapped I/O.

The 603e uses an advanced, 3.3 V CMOS process technology and maintains full interface compatibility with TTL devices.

3/38

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